OM11077 NXP Semiconductors, OM11077 Datasheet - Page 402

• Manufacturer Part Number: OM11077
• Description: MODULE DIMM LPC2478 ARM7
• Manufacturer: NXP Semiconductors

Specifications of OM11077

• Accessory Type: Module Card
• For Use With/related Products: ARM-57TS-LPC2478
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-4742

NXP Semiconductors
UM10237_4
User manual
7.2 OTG Interrupt Status Register (OTGIntSt - 0xE01F C100)
7.3 OTG Interrupt Enable Register (OTGIntEn - 0xFFE0 C104)
7.4 OTG Interrupt Set Register (OTGIntSet - 0xFFE0 C20C)
7.5 OTG Interrupt Clear Register (OTGIntClr - 0xFFE0 C10C)
7.6 OTG Status and Control Register (OTGStCtrl - 0xFFE0 C110)
Bits is this register are set by hardware when the interrupt event occurs during the HNP
handoff sequence. See
Table 364. OTG Interrupt Status register (OTGIntSt - address 0xE01F C100) bit description
Writing a one to a bit in this register enables the corresponding bit in OTGIntSt to generate
an interrupt on one of the interrupt lines. The interrupt is routed to the USB_OTG_INT
interrupt line in the USBIntSt register.
The bit allocation and reset value of OTGIntEn is the same as OTGIntSt.
Writing a one to a bit in this register will set the corresponding bit in the OTGIntSt register.
Writing a zero has no effect. The bit allocation of OTGIntSet is the same as in OTGIntSt.
Writing a one to a bit in this register will clear the corresponding bit in the OTGIntSt
register. Writing a zero has no effect. The bit allocation of OTGIntClr is the same as in
OTGIntSt.
The OTGStCtrl register allows enabling hardware tracking during the HNP hand over
sequence, controlling the OTG timer, monitoring the timer count, and controlling the
functions mapped to port U1 and U2.
Time critical events during the switching sequence are controlled by the OTG timer. The
timer can operate in two modes:
Bit
0
1
2
3
31:4
1. Monoshot mode: an interrupt is generated at the end of TIMEOUT_CNT (see
15–7.7 “OTG Timer Register (OTGTmr - 0xFFE0
OTGIntSt, and the timer will be disabled.
Symbol
TMR
REMOVE_PU
HNP_FAILURE
HNP_SUCCESS
-
Rev. 04 — 26 August 2009
Section 15–8
Description
Timer time-out.
Remove pull-up.
This bit is set by hardware to indicate that software
needs to disable the D+ pull-up resistor.
HNP failed.
This bit is set by hardware to indicate that the HNP
switching has failed.
HNP succeeded.
This bit is set by hardware to indicate that the HNP
switching has succeeded.
Reserved, user software should not write ones to
reserved bits. The value read from a reserved bit is not
defined.
for more information on when these bits are set.
Chapter 15: LPC24XX USB OTG controller
C114)”), the TMR bit is set in
UM10237
© NXP B.V. 2009. All rights reserved.
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Section
Reset
Value
0
0
0
0
NA