OM11077 NXP Semiconductors, OM11077 Datasheet - Page 667
OM11077
Manufacturer Part Number
OM11077
Description
MODULE DIMM LPC2478 ARM7
Manufacturer
NXP Semiconductors
Specifications of OM11077
Accessory Type
Module Card
For Use With/related Products
ARM-57TS-LPC2478
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
568-4742
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1. Basic configuration
2. Features
3. Description
4. Pin description
UM10237_4
User manual
The ADC is configured using the following registers:
Basic clocking for the A/D converters is provided by the APB clock (PCLK). A
programmable divider is included in each converter, to scale this clock to the 4.5 MHz
(max) clock needed by the successive approximation process. A fully accurate conversion
requires 11 of these clocks.
Table 28–591
1. Power: In the PCONP register
2. Clock: In the PCLK_SEL0 register
3. Pins: Select ADC pins and pin modes in registers PINSELn and PINMODEn (see
4. Interrupts: To enable interrupts in the ADC, see
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UM10237
Chapter 28: LPC24XX Analog-to Digital Converter (ADC)
Rev. 04 — 26 August 2009
Remark: On reset, the ADC is disabled. To enable the ADC, first set the PCADC bit,
and then enable the ADC in the AD0CR register (bit PDN)
the ADC, first clear the PDN bit, and then clear the PCADC bit.
clock for the ADC, see
Section
in the VIC using the VICIntEnable register
10 bit successive approximation analog to digital converter.
Input multiplexing among 8 pins.
Power-down mode.
Measurement range 0 to 3 V.
10 bit conversion time ≥ 2.44 μs.
Burst conversion mode for single or multiple inputs.
Optional conversion on transition on input pin or Timer Match signal.
Individual result registers for each A/D channel to reduce interrupt overhead.
9–5).
gives a brief summary of each of ADC related pins.
Rev. 04 — 26 August 2009
Table 28–593
(Table
(Table
bits CLKDIV.
4–63), set bits PCADC.
4–56), select PCLK_ADC. To scale the
(Section
Table
7–3.4).
28–596. Interrupts are enabled
Table
28–593. To disable
© NXP B.V. 2009. All rights reserved.
User manual
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