OM11077 NXP Semiconductors, OM11077 Datasheet - Page 322
OM11077
Manufacturer Part Number
OM11077
Description
MODULE DIMM LPC2478 ARM7
Manufacturer
NXP Semiconductors
Specifications of OM11077
Accessory Type
Module Card
For Use With/related Products
ARM-57TS-LPC2478
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
568-4742
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UM10237_4
User manual
7.25 Cursor Raw Interrupt Status register (CRSR_INTRAW, RW - 0xFFE1
7.26 Cursor Masked Interrupt Status register (CRSR_INTSTAT, RW -
0C28)
The CRSR_INTRAW register is set to indicate a cursor interrupt. When enabled via the
CrsrIM bit in the CRSR_INTMSK register, provides the interrupt to the system interrupt
controller.
The contents of the CRSR_INTRAW register are described in
Table 284. Cursor Raw Interrupt Status register (CRSR_INTRAW, RW - 0xFFE1 0C28)
0xFFE1 0C2C)
The CRSR_INTSTAT register is set to indicate a cursor interrupt providing that the
interrupt is not masked in the
The contents of the CRSR_INTSTAT register are described in
Table 285. Cursor Masked Interrupt Status register (CRSR_INTSTAT, RW - 0xFFE1 0C2C)
Bits
31:1
0
Bits
31:1
0
Function
reserved
CrsrRIS
Function
reserved
CrsrMIS
Rev. 04 — 26 August 2009
Description
Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.
Cursor raw interrupt status.
The cursor interrupt status is set immediately after the last data
is read from the cursor image for the current frame.
This bit is cleared by writing to the CrsrIC bit in the
CRSR_INTCLR register.
Description
Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.
Cursor masked interrupt status.
The cursor interrupt status is set immediately after the last data
read from the cursor image for the current frame, providing that
the corresponding bit in the CRSR_INTMSK register is set.
The bit remains clear if the CRSR_INTMSK register is clear.
This bit is cleared by writing to the CRSR_INTCLR register.
CRSR_INTMSK
register.
Chapter 12: LPC24XX LCD controller
Table
Table
12–284.
12–285.
UM10237
© NXP B.V. 2009. All rights reserved.
322 of 792
Reset
value
-
0x0
Reset
value
-
0x0
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