OM11077 NXP Semiconductors, OM11077 Datasheet - Page 630
OM11077
Manufacturer Part Number
OM11077
Description
MODULE DIMM LPC2478 ARM7
Manufacturer
NXP Semiconductors
Specifications of OM11077
Accessory Type
Module Card
For Use With/related Products
ARM-57TS-LPC2478
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
568-4742
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7. Example timer operation
8. Architecture
UM10237_4
User manual
Fig 129. A timer cycle in which PR=2, MRx=6, and both interrupt and reset on match are enabled.
Fig 130. A timer Cycle in Which PR=2, MRx=6, and both interrupt and stop on match are enabled
prescale counter
timer counter
(counter enable)
timer counter
prescale
interrupt
counter
counter
PCLK
timer
reset
interrupt
TCR[0]
PCLK
Figure 24–129
match. The prescaler is set to 2 and the match register set to 6. At the end of the timer
cycle where the match occurs, the timer count is reset. This gives a full length cycle to the
match value. The interrupt indicating that a match occurred is generated in the next clock
after the timer reached the match value.
Figure 24–130
prescaler is again set to 2 and the match register set to 6. In the next clock after the timer
reaches the match value, the timer enable bit in TCR is cleared, and the interrupt
indicating that a match occurred is generated.
The block diagram for TIMER/COUNTER0 and TIMER/COUNTER1 is shown in
Figure
4
2
4
2
24–131.
0
0
shows a timer configured to reset the count and generate an interrupt on
shows a timer configured to stop and generate an interrupt on match. The
1
5
1
5
1
Rev. 04 — 26 August 2009
2
2
0
0
1
6
6
0
2
0
Chapter 24: LPC24XX Timer0/1/2/3
1
0
2
0
UM10237
1
© NXP B.V. 2009. All rights reserved.
1
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