OM11077 NXP Semiconductors, OM11077 Datasheet - Page 617

• Manufacturer Part Number: OM11077
• Description: MODULE DIMM LPC2478 ARM7
• Manufacturer: NXP Semiconductors

Specifications of OM11077

• Accessory Type: Module Card
• For Use With/related Products: ARM-57TS-LPC2478
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-4742

NXP Semiconductors
6. I
UM10237_4
User manual
2
S transmit and receive interfaces
5.10 Receive Clock Rate Register (I2SRXRATE - 0xE008 8024)
5.9 Transmit Clock Rate Register (I2STXRATE - 0xE008 8020)
Table 539: Interrupt Request Control register (I2SIRQ - address 0xE008 801C) bit description
The bit rate for the I
The value depends on the audio sample rate desired, and the data size and format
(stereo/mono) used. For example, a 48 kHz sample rate for 16 bit stereo data requires a
bit rate of 48,000×16×2 = 1.536 MHz.
Table 540: Transmit Clock Rate register (I2TXRATE - address 0xE008 8020) bit description
The bit rate for the I
The value depends on the audio sample rate, as well as the data size and format used.
The calculation is the same as for I2STXRATE.
Table 541: Receive Clock Rate register (I2SRXRATE - address 0xE008 8024) bit description
The I
information. Some details of I
Bit
0
1
7:2
15:8
23:16
31:24
Bit
9:0
15:10
Bit
9:0
15:10
•
•
•
When the FIFO is empty, the transmit channel will repeat transmitting the same data
until new data is written to the FIFO.
When mute is true, the data value 0 is transmitted.
When mono is false, two successive data words are respectively left and right data.
2
S interface can transmit and receive 8, 16 or 32 bits stereo or mono audio
Symbol
rx_Irq_enable
tx_Irq_enable
Unused
rx_depth_Irq
tx_depth_Irq
-
Symbol
tx_rate
Unused
Symbol
rx_rate
Unused
Description
I
to produce the transmit bit clock. Ten bits of divide supports a wide
range of I
Unused.
Description
I
to produce the receive bit clock. Ten bits of divide supports a wide
range of I
Unused.
2
2
2
2
S transmitter is determined by the value of the I2STXRATE register.
S receiver is determined by the value of the I2SRXRATE register.
S transmit bit rate. This value plus one is used to divide PCLK by
S receive bit rate. This value plus one is used to divide PCLK by
Rev. 04 — 26 August 2009
2
2
Description
When 1, enables I2S receive interrupt.
When 1, enables I2S transmit interrupt.
Unused.
Set the FIFO level on which to create an irq request.
Reserved, user software should not write ones to
reserved bits. The value read from a reserved bit is not
defined.
Set the FIFO level on which to create an irq request.
S rates over a wide range of pclk rates.
S rates over a wide range of pclk rates.
2
S implementation are:
Chapter 23: LPC24XX I
UM10237
© NXP B.V. 2009. All rights reserved.
2
S interface
Reset
Value
0
0
0
0
0
NA
Reset
Value
0
0
Reset
Value
0
0
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