OM11077 NXP Semiconductors, OM11077 Datasheet - Page 309

• Manufacturer Part Number: OM11077
• Description: MODULE DIMM LPC2478 ARM7
• Manufacturer: NXP Semiconductors

Specifications of OM11077

• Accessory Type: Module Card
• For Use With/related Products: ARM-57TS-LPC2478
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-4742

NXP Semiconductors
UM10237_4
User manual
7.5 Line End Control register (LCD_LE, RW - 0xFFE1 000C)
Table 263. Clock and Signal Polarity register (LCD_POL, RW - 0xFFE1 0008)
The LCD_LE register controls the enabling of line-end signal LCDLE. When enabled, a
positive pulse, four LCDCLK periods wide, is output on LCDLE after a programmable
delay, LED, from the last pixel of each display line. If the line-end signal is disabled it is
held permanently LOW.
The contents of the LCD_LE register are described in
Bits
10:6
5
4:0
Function
ACB
CLKSEL
PCD_LO
Rev. 04 — 26 August 2009
Description
AC bias pin frequency.
The AC bias pin frequency is only applicable to STN displays.
These require the pixel voltage polarity to periodically reverse to
prevent damage caused by DC charge accumulation. Program
this field with the required value minus one to apply the number
of line clocks between each toggle of the AC bias pin,
LCDENAB. This field has no effect if the LCD is operating in TFT
mode, when the LCDENAB pin is used as a data enable signal.
Clock Select.
This bit controls the selection of the source for LCDCLK.
0 = the clock source for the LCD block is CCLK.
1 = the clock source for the LCD block is LCDCLKIN (external
clock input for the LVD).
Lower five bits of panel clock divisor.
The ten-bit PCD field, comprising PCD_HI (bits 31:27 of this
register) and PCD_LO, is used to derive the LCD panel clock
frequency LCDDCLK from the input clock, LCDDCLK =
LCDCLK/(PCD+2).
For monochrome STN displays with a 4 or 8-bit interface, the
panel clock is a factor of four and eight down from the actual
individual pixel clock rate. For color STN displays, 22/3 pixels
are output per LCDDCLK cycle, so the panel clock is 0.375 times
the pixel rate.
For TFT displays, the pixel clock divider can be bypassed by
setting the BCD bit in this register.
Note: data path latency forces some restrictions on the usable
minimum values for the panel clock divider in STN modes:
Single panel color mode, PCD = 1 (LCDDCLK = LCDCLK/3).
Dual panel color mode, PCD = 4 (LCDDCLK = LCDCLK/6).
Single panel monochrome 4-bit interface mode, PCD =
2(LCDDCLK = LCDCLK/4).
Dual panel monochrome 4-bit interface mode and single panel
monochrome 8-bit interface mode, PCD = 6(LCDDCLK =
LCDCLK/8).
Dual panel monochrome 8-bit interface mode, PCD =
14(LCDDCLK = LCDCLK/16).
Chapter 12: LPC24XX LCD controller
Table
12–264.
UM10237
© NXP B.V. 2009. All rights reserved.
309 of 792
Reset
value
0x0
0x0
0x0