OM11077 NXP Semiconductors, OM11077 Datasheet - Page 628

• Manufacturer Part Number: OM11077
• Description: MODULE DIMM LPC2478 ARM7
• Manufacturer: NXP Semiconductors

Specifications of OM11077

• Accessory Type: Module Card
• For Use With/related Products: ARM-57TS-LPC2478
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-4742

NXP Semiconductors
UM10237_4
User manual
6.10 Capture Control Register (T[0/1/2/3]CCR - 0xE000 4028, 0xE000 8028,
6.9 Capture Registers (CR0 - CR3)
Each Capture register is associated with a device pin and may be loaded with the Timer
Counter value when a specified event occurs on that pin. The settings in the Capture
Control Register register determine whether the capture function is enabled, and whether
a capture event happens on the rising edge of the associated pin, the falling edge, or on
both edges.
0xE007 0028, 0xE007 4028)
The Capture Control Register is used to control whether one of the four Capture Registers
is loaded with the value in the Timer Counter when the capture event occurs, and whether
an interrupt is generated by the capture event. Setting both the rising and falling bits at the
same time is a valid configuration, resulting in a capture event for both edges. In the
description below, "n" represents the Timer number, 0 or 1.
Note: If Counter mode is selected for a particular CAP input in the CTCR, the 3 bits for
that input in this register should be programmed as 000, but capture and/or interrupt can
be selected for the other 3 CAP inputs.
Table 551: Capture Control Register (T[0/1/2/3]CCR - addresses 0xE000 4028, 0xE000 8020,
Bit
0
1
2
3
4
5
15:6
Symbol
CAP0RE 1
CAP0FE 1
CAP0I
CAP1RE 1
CAP1FE 1
CAP1I
-
0xE007 0028, 0xE007 4028) bit description
Value Description
0
0
1
0
0
0
1
0
Rev. 04 — 26 August 2009
Capture on CAPn.0 rising edge: a sequence of 0 then 1 on
CAPn.0 will cause CR0 to be loaded with the contents of TC.
This feature is disabled.
Capture on CAPn.0 falling edge: a sequence of 1 then 0 on
CAPn.0 will cause CR0 to be loaded with the contents of TC.
This feature is disabled.
Interrupt on CAPn.0 event: a CR0 load due to a CAPn.0 event
will generate an interrupt.
This feature is disabled.
Capture on CAPn.1 rising edge: a sequence of 0 then 1 on
CAPn.1 will cause CR1 to be loaded with the contents of TC.
This feature is disabled.
Capture on CAPn.1 falling edge: a sequence of 1 then 0 on
CAPn.1 will cause CR1 to be loaded with the contents of TC.
This feature is disabled.
Interrupt on CAPn.1 event: a CR1 load due to a CAPn.1 event
will generate an interrupt.
This feature is disabled.
Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.
Chapter 24: LPC24XX Timer0/1/2/3
UM10237
© NXP B.V. 2009. All rights reserved.
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Reset
Value
0
0
0
0
0
0
NA