OM11077 NXP Semiconductors, OM11077 Datasheet - Page 113

• Manufacturer Part Number: OM11077
• Description: MODULE DIMM LPC2478 ARM7
• Manufacturer: NXP Semiconductors

Specifications of OM11077

• Accessory Type: Module Card
• For Use With/related Products: ARM-57TS-LPC2478
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-4742

NXP Semiconductors
UM10237_4
User manual
3.4 Interrupt Enable Register (VICIntEnable - 0xFFFF F010)
3.5 Interrupt Enable Clear Register (VICIntEnClear - 0xFFFF F014)
3.6 Interrupt Select Register (VICIntSelect - 0xFFFF F00C)
Table 105. Raw Interrupt Status register (VICRawIntr - address 0xFFFF F008) bit description
This is a read/write accessible register. This register controls which of the 32 combined
hardware and software interrupt requests are enabled to contribute to FIQ or IRQ.
Table 106. Interrupt Enable register (VICIntEnable - address 0xFFFF F010) bit description
This is a write only register. This register allows software to clear one or more bits in the
Interrupt Enable register (see
0xFFFF F010)” on page
Table 107. Interrupt Enable Clear register (VICIntEnClear - address 0xFFFF F014) bit
This is a read/write accessible register. This register classifies each of the 32 interrupt
requests as contributing to FIQ or IRQ.
Bit
31:0 See
Bit
31:0 See
Bit
31:0 See
Symbol
7–117
“Interrupt
sources bit
allocation
table”.
Symbol
7–117
“Interrupt
sources bit
allocation
table”.
Symbol
7–117
“Interrupt
sources bit
allocation
table”.
Table
Table
Table
description
Description
When this register is read, 1s indicate interrupt requests or software
interrupts that are enabled to contribute to FIQ or IRQ.
When this register is written, ones enable interrupt requests or
software interrupts to contribute to FIQ or IRQ, zeroes have no
effect. See
(VICIntEnClear - 0xFFFF F014)” on page 113
below for how to disable interrupts.
Value Description
0
1
Value Description
0
1
Rev. 04 — 20 August 2009
113), without having to first read it.
Neither the hardware nor software interrupt request with this
bit number are asserted.
The hardware or software interrupt request with this bit
number is asserted.
Writing a 0 leaves the corresponding bit in VICIntEnable
unchanged.
Writing a 1 clears the corresponding bit in the Interrupt
Enable register, thus disabling interrupts for this request.
Section 7–3.4 “Interrupt Enable Register (VICIntEnable -
Chapter 7: LPC24XX Vectored Interrupt Controller (VIC)
Section 7–3.5 “Interrupt Enable Clear Register
and
Table 7–107
UM10237
© NXP B.V. 2009. All rights reserved.
113 of 792
Reset
value
-
Reset
value
-
Reset
value
0