OM11077 NXP Semiconductors, OM11077 Datasheet - Page 34
OM11077
Manufacturer Part Number
OM11077
Description
MODULE DIMM LPC2478 ARM7
Manufacturer
NXP Semiconductors
Specifications of OM11077
Accessory Type
Module Card
For Use With/related Products
ARM-57TS-LPC2478
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
568-4742
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UM10237_4
User manual
3.3.1 AHB Arbiter Configuration register 1 (AHBCFG1 - 0xE01F C188)
3.3 AHB Configuration
Table 28.
The AHB configuration register allows changing AHB scheduling and arbitration
strategies.
Table 29.
By default, the AHB1 access is scheduled round-robin (bit 0 = 1). For round-robin
scheduling, the default priority sequence will be CPU, DMA, AHB1, USB and LCD.
The AHB1 access priority can be configured as priority scheduling (bit 0 = 0) and priority
of the each of the AHB1 bus masters can be set by writing the priority value (highest
priority = 5, lowest priority = 1).
Masters with the same priority value are scheduled on a round-robin basis.
Bit
0
1
2
3
7:4
Name
AHBCFG1 Configures the AHB1 arbiter.
AHBCFG2 Configures the AHB2 arbiter.
Symbol Description
POR
EXTR
WDTR
BODR
-
Reset Source Identification register (RSID - address 0xE01F C180) bit description
AHB configuration register map
Description
Assertion of the POR signal sets this bit, and clears all of the other bits in
this register. But if another Reset signal (e.g., External Reset) remains
asserted after the POR signal is negated, then its bit is set. This bit is not
affected by any of the other sources of Reset.
Assertion of the RESET signal sets this bit. This bit is cleared by POR,
but is not affected by WDT or BOD reset.
This bit is set when the Watchdog Timer times out and the WDTRESET
bit in the Watchdog Mode Register is 1. It is cleared by any of the other
sources of Reset.
This bit is set when the 3.3 V power reaches a level below 2.6 V.
If the V
BODR bit will be set to 1.
If the V
decline to the level at which POR is asserted (nominally 1 V), the BODR
bit is cleared.
if the V
above 2.6 V, the BODR will be set to 1.
This bit is not affected by External Reset nor Watchdog Reset.
Note: Only in case when a reset occurs and the POR = 0, the BODR bit
indicates if the V
Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.
DD(DCDC)(3V3)
DD(DCDC)(3V3)
DD(DCDC)(3V3)
Rev. 04 — 26 August 2009
DD(DCDC)(3V3)
voltage rises continuously from below 1 V to a level
voltage dips from 3.3 V to 2.5 V and backs up, the
voltage dips from 3.3 V to 2.5 V and continues to
voltage was below 2.6 V or not.
Access
R/W
R/W
Chapter 3: LPC24XX System control
Reset value
0x0000 0145
0x0000 0145
UM10237
© NXP B.V. 2009. All rights reserved.
Address
0xE01F C188
0xE01F C18C
Reset
value
See text
See text
See text
See text
NA
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