OM11077 NXP Semiconductors, OM11077 Datasheet - Page 651

• Manufacturer Part Number: OM11077
• Description: MODULE DIMM LPC2478 ARM7
• Manufacturer: NXP Semiconductors

Specifications of OM11077

• Accessory Type: Module Card
• For Use With/related Products: ARM-57TS-LPC2478
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-4742

NXP Semiconductors
UM10237_4
User manual
6.2.2 Clock Tick Counter Register (CTCR - 0xE002 4004)
6.2.3 Clock Control Register (CCR - 0xE002 4008)
6.2.4 Counter Increment Interrupt Register (CIIR - 0xE002 400C)
The Clock Tick Counter is read only. It can be reset to zero through the Clock Control
Register (CCR). The CTC consists of the bits of the clock divider counter.
Table 568. Clock Tick Counter Register (CTCR - address 0xE002 4004) bit description
If the RTC is driven by the external 32.786 kHz oscillator, subsequent read operations of
the CTCR may yield an incorrect result. The CTCR is implemented as a 15-bit ripple
counter so that not all 15 bits change simultaneously. The LSB changes first, then the
next, and so forth. Since the 32.786 kHz oscillator is asynchronous to the CPU clock, it is
possible for a CTC read to occur during the time when the CTCR bits are changing
resulting in an incorrect large difference between back-to-back reads.
If the RTC is driven by the PCLK, the CPU and the RTC are synchronous because both of
their clocks are driven from the PLL output. Therefore, incorrect consecutive reads can
not occur.
The clock register controls the operation of the clock divide circuit. Each bit of the clock
register is described in
Table 569. Clock Control Register (CCR - address 0xE002 4008) bit description
The Counter Increment Interrupt Register (CIIR) gives the ability to generate an interrupt
every time a counter is incremented. This interrupt remains valid until cleared by writing a
one to bit zero of the Interrupt Location Register (ILR[0]).
Bit
0
15:1
Bit
0
1
3:2
4
7:5
Symbol
-
Clock Tick
Counter
Symbol
CLKEN
CTCRST
-
CLKSRC
-
Description
Clock Enable. When this bit is a one the time counters are enabled.
When it is a zero, they are disabled so that they may be initialized.
CTC Reset. When one, the elements in the Clock Tick Counter are
reset. The elements remain reset until CCR[1] is changed to zero.
Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.
If this bit is 0, the Clock Tick Counter takes its clock from the Prescaler,
as on earlier devices in the NXP Embedded ARM family. If this bit is 1,
the CTC takes its clock from the 32 kHz oscillator that’s connected to
the RTCX1 and RTCX2 pins (see
oscillator component selection”
Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.
Description
Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.
Prior to the Seconds counter, the CTC counts 32,768 clocks per
second. Due to the RTC Prescaler, these 32,768 time increments may
not all be of the same duration. Refer to the
“Reference Clock Divider (Prescaler)” on page 656
Rev. 04 — 26 August 2009
Chapter 26: LPC24XX Real-Time Clock (RTC) and battery RAM
Table
26–569.
for hardware details).
Section 26–9 “RTC external 32 kHz
Section 26–6.7.1
for details.
UM10237
© NXP B.V. 2009. All rights reserved.
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Reset
value
NA
NA
Reset
value
NA
NA
NA
NA
NA