OM11077 NXP Semiconductors, OM11077 Datasheet - Page 626

• Manufacturer Part Number: OM11077
• Description: MODULE DIMM LPC2478 ARM7
• Manufacturer: NXP Semiconductors

Specifications of OM11077

• Accessory Type: Module Card
• For Use With/related Products: ARM-57TS-LPC2478
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-4742

NXP Semiconductors
UM10237_4
User manual
6.4 Timer Counter registers (T0TC - T3TC, 0xE000 4008, 0xE000 8008,
6.5 Prescale register (T0PR - T3PR, 0xE000 400C, 0xE000 800C,
6.6 Prescale Counter register (T0PC - T3PC, 0xE000 4010, 0xE000 8010,
6.7 Match Registers (MR0 - MR3)
Table 549: Count Control Register (T[0/1/2/3]CTCR - addresses 0xE000 4070, 0xE000 8070,
0xE007 0008, 0xE007 4008)
The 32-bit Timer Counter register is incremented when the prescale counter reaches its
terminal count. Unless it is reset before reaching its upper limit, the Timer Counter will
count up through the value 0xFFFF FFFF and then wrap back to the value 0x0000 0000.
This event does not cause an interrupt, but a match register can be used to detect an
overflow if needed.
0xE007 000C, 0xE007 400C)
The 32-bit Prescale register specifies the maximum value for the Prescale Counter.
0xE007 0010, 0xE007 4010)
The 32-bit Prescale Counter controls division of PCLK by some constant value before it is
applied to the Timer Counter. This allows control of the relationship of the resolution of the
timer versus the maximum time before the timer overflows. The Prescale Counter is
incremented on every PCLK. When it reaches the value stored in the Prescale register,
the Timer Counter is incremented and the Prescale Counter is reset on the next PCLK.
This causes the Timer Counter to increment on every PCLK when PR = 0, every 2 PCLKs
when PR = 1, etc.
The Match register values are continuously compared to the Timer Counter value. When
the two values are equal, actions can be triggered automatically. The action possibilities
are to generate an interrupt, reset the Timer Counter, or stop the timer. Actions are
controlled by the settings in the MCR register.
Bit
3:2
7:4
Symbol
Count
Input
Select
-
0xE007 0070, 0xE007 4070) bit description
Value
00
01
10
11
-
Rev. 04 — 26 August 2009
Description
When bits 1:0 in this register are not 00, these bits select
which CAP pin is sampled for clocking:
CAPn.0 for TIMERn
CAPn.1 for TIMERn
Note: If Counter mode is selected for a particular CAPn input
in the TnCTCR, the 3 bits for that input in the Capture
Control Register (TnCCR) must be programmed as 000.
However, capture and/or interrupt can be selected for the
other 3 CAPn inputs in the same timer.
Reserved.
Reserved.
Reserved, user software should not write ones to reserved
bits. The value read from a reserved bit is not defined.
Chapter 24: LPC24XX Timer0/1/2/3
UM10237
© NXP B.V. 2009. All rights reserved.
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Reset
Value
00
NA