OM11077 NXP Semiconductors, OM11077 Datasheet - Page 88

• Manufacturer Part Number: OM11077
• Description: MODULE DIMM LPC2478 ARM7
• Manufacturer: NXP Semiconductors

Specifications of OM11077

• Accessory Type: Module Card
• For Use With/related Products: ARM-57TS-LPC2478
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-4742

NXP Semiconductors
UM10237_4
User manual
10.18 Static Memory Extended Wait register (EMCStaticExtendedWait -
10.19 Dynamic Memory Configuration registers (EMCDynamicConfig0-3 -
Table 84.
0xFFE0 8080)
ExtendedWait (EW) bit in the EMCStaticConfig register is set. It is recommended that this
register is modified during system initialization, or when there are no current or
outstanding transactions. However, if necessary, these control bits can be altered during
normal operation. This register is accessed with one wait state.
Table 5–85
Table 85.
For example, for a static memory read/write transfer time of 16 µs, and a CCLK frequency
of 50 MHz, the following value must be programmed into this register: (16 x 10-6 x 50 x
106) / 16 - 1 = 49
0xFFE0 8100, 120, 140, 160)
The EMCDynamicConfig0-3 registers enable you to program the configuration information
for the relevant dynamic memory chip select. These registers are normally only modified
during system initialization. These registers are accessed with one wait state.
Table 5–86
Bit
3:0
31:4
Bit
9:0
31:10 -
Symbol
Load mode
register to active
command time
(tMRD)
-
Symbol
Extended wait time
out
(EXTENDEDWAIT)
Dynamic Memory Load Mode register to Active Command Time
(EMCDynamictMRD - address 0xFFE0 8058) bit description
Static Memory Extended Wait register (EMCStaticExtendedWait - address
0xFFE0 8080) bit description
shows the bit assignments for the EMCStaticExtendedWait registers.
shows the bit assignments for the EMCDynamicConfig0-3 registers.
Rev. 04 — 26 August 2009
0x0 -
0xE
0xF
Value Description
-
Value Description
0x0
0x1
-
Chapter 5: LPC24XX External Memory Controller (EMC)
n + 1 clock cycles. The delay is in CCLK cycles.
16 clock cycles (POR reset value).
Reserved, user software should not write ones to
reserved bits. The value read from a reserved bit is not
defined.
16 clock cycles (POR reset value). The delay is in
CCLK cycles.
(n+1) x16 clock cycles.
Reserved, user software should not write ones to
reserved bits. The value read from a reserved bit is
not defined.
UM10237
© NXP B.V. 2009. All rights reserved.
88 of 792
Reset
Value
0xF
NA
Reset
Value
NA