OM11077 NXP Semiconductors, OM11077 Datasheet - Page 236

• Manufacturer Part Number: OM11077
• Description: MODULE DIMM LPC2478 ARM7
• Manufacturer: NXP Semiconductors

Specifications of OM11077

• Accessory Type: Module Card
• For Use With/related Products: ARM-57TS-LPC2478
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-4742

NXP Semiconductors
UM10237_4
User manual
7.2.17 Flow Control Status Register (FlowControlStatus - 0xFFE0 0174)
7.3.1 Receive Filter Control Register (RxFilterCtrl - 0xFFE0 0200)
7.3 Receive filter register definitions
Table 221. Flow Control Counter register (FlowControlCounter - address 0xFFE0 0170) bit
The Flow Control Status register (FlowControlStatus) is a Read Only register with an
address of 0xFFE0 8174.
Table 222. Flow Control Status register (FlowControlStatus - address 0xFFE0 8174) bit
The Receive Filter Control register (RxFilterCtrl) has an address of 0xFFE0 0200.
Table 11–223
Table 223. Receive Filter Control register (RxFilterCtrl - address 0xFFE0 0200) bit
Bit
15:0
31:16
Bit
15:0
31:16
Bit
0
1
2
3
4
5
11:6
Symbol
AcceptUnicastEn
AcceptBroadcastEn
AcceptMulticastEn
AcceptUnicastHashEn
AcceptMulticastHashEn
AcceptPerfectEn
-
Symbol
MirrorCounter
PauseTimer
Symbol
MirrorCounterCurrent In full duplex mode this register represents the current
-
description
description
description
lists the definition of the individual bits in the register.
Rev. 04 — 26 August 2009
Table 11–222
Function
In full duplex mode the MirrorCounter specifies the number
of cycles before re-issuing the Pause control frame.
In full-duplex mode the PauseTimer specifies the value
that is inserted into the pause timer field of a pause flow
control frame. In half duplex mode the PauseTimer
specifies the number of backpressure cycles.
Function
value of the datapath’s mirror counter which counts up to
the value specified by the MirrorCounter field in the
FlowControlCounter register. In half duplex mode the
register counts until it reaches the value of the PauseTimer
bits in the FlowControlCounter register.
Unused
When set to ’1’, multicast frames that pass the
Function
When set to ’1’, all unicast frames are accepted.
When set to ’1’, all broadcast frames are accepted.
When set to ’1’, all multicast frames are accepted.
When set to ’1’, unicast frames that pass the imperfect
hash filter are accepted.
imperfect hash filter are accepted.
When set to ’1’, the frames with a destination address
identical to the
station address are accepted.
Reserved, user software should not write ones to
reserved bits. The value read from a reserved bit is not
defined.
lists the bit definitions of the register.
Chapter 11: LPC24XX Ethernet
UM10237
© NXP B.V. 2009. All rights reserved.
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Reset
value
0
0
0
0
0
0
NA
Reset
value
0x0
0x0
Reset
value
0x0
0x0