OM11077 NXP Semiconductors, OM11077 Datasheet - Page 220

• Manufacturer Part Number: OM11077
• Description: MODULE DIMM LPC2478 ARM7
• Manufacturer: NXP Semiconductors

Specifications of OM11077

• Accessory Type: Module Card
• For Use With/related Products: ARM-57TS-LPC2478
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-4742

NXP Semiconductors
UM10237_4
User manual
7.1 Ethernet MAC register definitions
Table 186. Summary of Ethernet registers
The third column in the table lists the accessibility of the register: read-only, write-only,
read/write.
All AHB register write transactions except for accesses to the interrupt registers are
posted i.e. the AHB transaction will complete before write data is actually committed to the
register. Accesses to the interrupt registers will only be completed by accepting the write
data when the data has been committed to the register.
This section defines the bits in the individual registers of the Ethernet block register map.
Symbol
RSV
-
FlowControlCounter
FlowControlStatus
-
Rx filter registers
RxFliterCtrl
RxFilterWoLStatus
RxFilterWoLClear
-
HashFilterL
HashFilterH
-
Module control registers
IntStatus
IntEnable
IntClear
IntSet
-
PowerDown
-
Address
0xFFE0 0160
0xFFE0 0164 to
0xFFE0 016C
0xFFE0 0170
0xFFE0 0174
0xFFE0 0178 to
0xFFE0 01FC
0xFFE0 0200
0xFFE0 0204
0xFFE0 0208
0xFFE0 020C
0xFFE0 0210
0xFFE0 0218 to
0xFFE0 0FDC
0xFFE0 0FE0
0xFFE0 0FE4
0xFFE0 0FE8
0xFFE0 0FEC
0xFFE0 0FF0
0xFFE0 0FF4
0xFFE0 0FF8
0xFFE0 0214
Rev. 04 — 26 August 2009
R/W Description
RO
-
R/W Flow control counter register.
RO
-
-
-
RO
R/W Interrupt enable register.
WO Interrupt clear register.
WO Interrupt set register.
-
R/W Power-down register.
-
Receive status vector register.
Reserved, user software should not write ones to
reserved bits. The value read from a reserved bit
is not defined.
Flow control status register.
Reserved, user software should not write ones to
reserved bits. The value read from a reserved bit
is not defined.
Receive filter control register.
Receive filter WoL status register.
Receive filter WoL clear register.
Reserved, user software should not write ones to
reserved bits. The value read from a reserved bit
is not defined.
Hash filter table LSBs register.
Hash filter table MSBs register.
Reserved, user software should not write ones to
reserved bits. The value read from a reserved bit
is not defined.
Interrupt status register.
Reserved, user software should not write ones to
reserved bits. The value read from a reserved bit
is not defined.
Reserved, user software should not write ones to
reserved bits. The value read from a reserved bit
is not defined.
Chapter 11: LPC24XX Ethernet
UM10237
© NXP B.V. 2009. All rights reserved.
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