OM11077 NXP Semiconductors, OM11077 Datasheet - Page 29

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OM11077

Manufacturer Part Number
OM11077
Description
MODULE DIMM LPC2478 ARM7
Manufacturer
NXP Semiconductors
Datasheets

Specifications of OM11077

Accessory Type
Module Card
For Use With/related Products
ARM-57TS-LPC2478
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
568-4742
NXP Semiconductors
UM10237_4
User manual
Once a bit from EINT0 to EINT3 is set and an appropriate code starts to execute (handling
wakeup and/or external interrupt), this bit in EXTINT register must be cleared. Otherwise
event that was just triggered by activity on the EINT pin will not be recognized in future.
Important: whenever a change of external interrupt operating mode (i.e. active
level/edge) is performed (including the initialization of an external interrupt),
corresponding bit in the EXTINT register must be cleared! For details see
3–3.1.3 “External Interrupt Mode register (EXTMODE - 0xE01F C148)”
3–3.1.4 “External Interrupt Polarity register (EXTPOLAR - 0xE01F
For example, if a system wakes up from power-down using low level on external interrupt
0 pin, its post-wakeup code must reset EINT0 bit in order to allow future entry into the
power-down mode. If EINT0 bit is left set to 1, subsequent attempt(s) to invoke
power-down mode will fail. The same goes for external interrupt handling.
More details on power-down mode will be discussed in the following chapters.
Table 25.
[1]
Bit Symbol Description
0
1
2
3
7:4 -
Example: If the EINTx is selected to be low level sensitive and low level is present on corresponding pin,
this bit can not be cleared; this bit can be cleared only when signal on the pin becomes high.
EINT0
EINT1
EINT2
EINT3
External Interrupt Flag register (EXTINT - address 0xE01F C140) bit description
In level-sensitive mode, this bit is set if the EINT0 function is selected for its
pin, and the pin is in its active state. In edge-sensitive mode, this bit is set if
the EINT0 function is selected for its pin, and the selected edge occurs on
the pin.
This bit is cleared by writing a one to it, except in level sensitive mode when
the pin is in its active state.
In level-sensitive mode, this bit is set if the EINT1 function is selected for its
pin, and the pin is in its active state. In edge-sensitive mode, this bit is set if
the EINT1 function is selected for its pin, and the selected edge occurs on
the pin.
This bit is cleared by writing a one to it, except in level sensitive mode when
the pin is in its active state.
In level-sensitive mode, this bit is set if the EINT2 function is selected for its
pin, and the pin is in its active state. In edge-sensitive mode, this bit is set if
the EINT2 function is selected for its pin, and the selected edge occurs on
the pin.
This bit is cleared by writing a one to it, except in level sensitive mode when
the pin is in its active state.
In level-sensitive mode, this bit is set if the EINT3 function is selected for its
pin, and the pin is in its active state. In edge-sensitive mode, this bit is set if
the EINT3 function is selected for its pin, and the selected edge occurs on
the pin.
This bit is cleared by writing a one to it, except in level sensitive mode when
the pin is in its active state.
Reserved, user software should not write ones to reserved bits. The value
read from a reserved bit is not defined.
Rev. 04 — 26 August 2009
[1]
[1]
[1]
[1]
Chapter 3: LPC24XX System control
C14C)”.
UM10237
© NXP B.V. 2009. All rights reserved.
and
Section
Section
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Reset
value
0
0
0
0
NA

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