OM11077 NXP Semiconductors, OM11077 Datasheet - Page 548

• Manufacturer Part Number: OM11077
• Description: MODULE DIMM LPC2478 ARM7
• Manufacturer: NXP Semiconductors

Specifications of OM11077

• Accessory Type: Module Card
• For Use With/related Products: ARM-57TS-LPC2478
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-4742

NXP Semiconductors
UM10237_4
User manual
6.4 SSPn Status Register (SSP0SR - 0xE006 800C, SSP1SR -
6.5 SSPn Clock Prescale Register (SSP0CPSR - 0xE006 8010, SSP1CPSR
6.6 SSPn Interrupt Mask Set/Clear Register (SSP0IMSC - 0xE006 8014,
0xE003 000C)
This read-only register reflects the current status of the SSP controller.
Table 474: SSPn Status Register (SSP0SR - address 0xE006 800C, SSP1SR - 0xE003 000C)
- 0xE003 0010)
This register controls the factor by which the Prescaler divides the SSP peripheral clock
SSP_PCLK to yield the prescaler clock that is, in turn, divided by the SCR factor in
SSPnCR0, to determine the bit clock.
Table 475: SSPn Clock Prescale Register (SSP0CPSR - address 0xE006 8010, SSP1CPSR -
Important: the SSPnCPSR value must be properly initialized or the SSP controller will not
be able to transmit data correctly.
In Slave mode, the SSP clock rate provided by the master must not exceed 1/12 of the
SSP peripheral clock selected in
is not relevant.
In master mode, CPSDVSR
SSP1IMSC - 0xE003 0014)
This register controls whether each of the four possible interrupt conditions in the SSP
controller are enabled. Note that ARM uses the word “masked” in the opposite sense from
classic computer terminology, in which “masked” meant “disabled”. ARM uses the word
“masked” to mean “enabled”. To avoid confusion we will not use the word “masked”.
Bit
0
1
2
3
4
7:5
Bit
7:0
Symbol
TFE
TNF
RNE
RFF
BSY
-
Symbol
CPSDVSR This even value between 2 and 254, by which SSP_PCLK is
bit description
0xE003 8010) bit description
Description
Transmit FIFO Empty. This bit is 1 is the Transmit FIFO is
empty, 0 if not.
Transmit FIFO Not Full. This bit is 0 if the Tx FIFO is full, 1 if not. 1
Receive FIFO Not Empty. This bit is 0 if the Receive FIFO is
empty, 1 if not.
Receive FIFO Full. This bit is 1 if the Receive FIFO is full, 0 if
not.
Busy. This bit is 0 if the SSPn controller is idle, or 1 if it is
currently sending/receiving a frame and/or the Tx FIFO is not
empty.
Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.
Description
divided to yield the prescaler output clock. Bit 0 always reads
as 0.
Rev. 04 — 26 August 2009
min
= 2 or larger (even numbers only).
Section
4–3.3.4. The content of the SSPnCPSR register
Chapter 20: LPC24XX SSP interface SSP0/1
UM10237
© NXP B.V. 2009. All rights reserved.
Reset Value
0
Reset Value
1
0
0
0
NA
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