OM11077 NXP Semiconductors, OM11077 Datasheet - Page 669

• Manufacturer Part Number: OM11077
• Description: MODULE DIMM LPC2478 ARM7
• Manufacturer: NXP Semiconductors

Specifications of OM11077

• Accessory Type: Module Card
• For Use With/related Products: ARM-57TS-LPC2478
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-4742

NXP Semiconductors
Table 593: A/D Control Register (AD0CR - address 0xE003 4000) bit description
UM10237_4
User manual
Bit
7:0
15:8
16
Symbol
SEL
CLKDIV
BURST
5.1 A/D Control Register (AD0CR - 0xE003 4000)
Value Description
0
1
Table 592. Summary of ADC registers
[1]
The A/D Control Register provides bits to select A/D channels to be converted, A/D timing,
A/D modes, and the A/D start trigger.
Name
AD0DR3
AD0DR4
AD0DR5
AD0DR6
AD0DR7
Selects which of the AD0.7:0 pins is (are) to be sampled and converted. For AD0, bit 0
selects Pin AD0.0, and bit 7 selects pin AD0.7. In software-controlled mode, only one of
these bits should be 1. In hardware scan mode, any value containing 1 to 8 ones. All
zeroes is equivalent to 0x01.
The APB clock (PCLK) is divided by (this value plus one) to produce the clock for the A/D
converter, which should be less than or equal to 4.5 MHz. Typically, software should
program the smallest value in this field that yields a clock of 4.5 MHz or slightly less, but in
certain cases (such as a high-impedance analog source) a slower clock may be
desirable.
Conversions are software controlled and require 11 clocks.
The AD converter does repeated conversions at the rate selected by the CLKS field,
scanning (if necessary) through the pins selected by 1s in the SEL field. The first
conversion after the start corresponds to the least-significant 1 in the SEL field, then
higher numbered 1 bits (pins) if applicable. Repeated conversions can be terminated by
clearing this bit, but the conversion that’s in progress when this bit is cleared will be
completed.
Important: START bits must be 000 when BURST = 1 or conversions will not start.
Reset Value reflects the data stored in used bits only. It does not include reserved bits content.
Description
A/D Channel 3 Data Register. This register
contains the result of the most recent
conversion completed on channel 3.
A/D Channel 4 Data Register. This register
contains the result of the most recent
conversion completed on channel 4.
A/D Channel 5 Data Register. This register
contains the result of the most recent
conversion completed on channel 5.
A/D Channel 6 Data Register. This register
contains the result of the most recent
conversion completed on channel 6.
A/D Channel 7 Data Register. This register
contains the result of the most recent
conversion completed on channel 7.
Rev. 04 — 26 August 2009
Chapter 28: LPC24XX Analog-to Digital Converter (ADC)
Access Reset
R/W
R/W
R/W
R/W
R/W
Value
NA
NA
NA
NA
NA
[1]
UM10237
© NXP B.V. 2009. All rights reserved.
Address
0xE003 401C
0xE003 4020
0xE003 4024
0xE003 4028
0xE003 402C
669 of 792
Reset
Value
0x01
0
0