OM11077 NXP Semiconductors, OM11077 Datasheet - Page 755

• Manufacturer Part Number: OM11077
• Description: MODULE DIMM LPC2478 ARM7
• Manufacturer: NXP Semiconductors

Specifications of OM11077

• Accessory Type: Module Card
• For Use With/related Products: ARM-57TS-LPC2478
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-4742

NXP Semiconductors
UM10237_4
User manual
; /*********************************************************************
; * Setup Vectored Interrupt controller. DCC Rx and Tx interrupts
; * generate Non Vectored IRQ request. rm_init_entry is aware
; * of the VIC and it enables the DBGCommRX and DBGCommTx interrupts.
; * Default vector address register is programmed with the address of
; * Non vectored app_irqDispatch mentioned in this example. User can setup
; * Vectored IRQs or FIQs here.
; *********************************************************************/
; /*********************************************************************
; * Get the address of the User entry point.
; *********************************************************************/
; /*********************************************************************
; * Non vectored irq handler (app_irqDispatch)
; *********************************************************************/
AREA app_irqDispatch, CODE
VICVectAddrOffset EQU 0x30
app_irqDispatch
;User should insert code here if non vectored Interrupt sharing is
;required. Each non vectored shared irq handler must return to
;the interrupted instruction by using the following code.
;
;
;
;
;
;
;
VICBaseAddr
VICDefVectAddrOffset EQU 0x34
LDR
LDR
STR
BL
;enable FIQ and IRQ in ARM Processor
MRS
BIC
MSR
LDR
MOV
;enable interrupt nesting
STMFD sp!, {r12,r14}
MRS
MSR
MSR
MSR
STMFD sp!, {r0}
LDR
STR
LDMFD sp!, {r12,r14,r0}
SUBS pc, r14, #4
;user interrupt did not happen so call rm_irqhandler2. This handler
r0, =VICBaseAddr
r1, =app_irqDispatch
r1, [r0,#VICDefVectAddrOffset]
rm_init_entry
r1, CPSR
r1, r1, #0xC0
CPSR_c, r1
lr, =User_Entry
pc, lr
r12, spsr
cpsr_c,0x1F
cpsr_c, #0x52
spsr, r12
r0, =VICBaseAddr
r1, [r0,#VICVectAddrOffset]
Rev. 04 — 26 August 2009
EQU 0xFFFFF000 ; VIC Base address
;Initialize RealMonitor
; get the CPSR
; enable IRQs and FIQs
; update the CPSR
;Save SPSR in to r12
;Re-enable IRQ, go to system mode
;Disable irq, move to IRQ mode
;Restore SPSR from r12
;Acknowledge Non Vectored irq has finished
;Restore registers
;Return to the interrupted instruction
Chapter 35: LPC24XX RealMonitor
UM10237
© NXP B.V. 2009. All rights reserved.
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