OM11077 NXP Semiconductors, OM11077 Datasheet - Page 430

• Manufacturer Part Number: OM11077
• Description: MODULE DIMM LPC2478 ARM7
• Manufacturer: NXP Semiconductors

Specifications of OM11077

• Accessory Type: Module Card
• For Use With/related Products: ARM-57TS-LPC2478
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-4742

NXP Semiconductors
UM10237_4
User manual
The UARTn RDA interrupt (UnIIR[3:1] = 010) shares the second level priority with the CTI
interrupt (UnIIR[3:1] = 110). The RDA is activated when the UARTn Rx FIFO reaches the
trigger level defined in UnFCR[7:6] and is reset when the UARTn Rx FIFO depth falls
below the trigger level. When the RDA interrupt goes active, the CPU can read a block of
data defined by the trigger level.
The CTI interrupt (UnIIR[3:1] = 110) is a second level interrupt and is set when the UARTn
Rx FIFO contains at least one character and no UARTn Rx FIFO activity has occurred in
3.5 to 4.5 character times. Any UARTn Rx FIFO activity (read or write of UARTn RSR) will
clear the interrupt. This interrupt is intended to flush the UARTn RBR after a message has
been received that is not a multiple of the trigger level size. For example, if a peripheral
wished to send a 105 character message and the trigger level was 10 characters, the
CPU would receive 10 RDA interrupts resulting in the transfer of 100 characters and 1 to 5
CTI interrupts (depending on the service routine) resulting in the transfer of the remaining
5 characters.
Table 384. UARTn Interrupt Handling
[1]
[2]
[3]
[4]
The UARTn THRE interrupt (UnIIR[3:1] = 001) is a third level interrupt and is activated
when the UARTn THR FIFO is empty provided certain initialization conditions have been
met. These initialization conditions are intended to give the UARTn THR FIFO a chance to
fill up with data to eliminate many THRE interrupts from occurring at system start-up. The
initialization conditions implement a one character delay minus the stop bit whenever
U0IIR[3:0]
value
0001
0110
0100
1100
0010
Values "0000", “0011”, “0101”, “0111”, “1000”, “1001”, “1010”, “1011”,”1101”,”1110”,”1111” are reserved.
For details see
0xE007 8014, U3LSR - 0xE007 C014, Read Only)”
For details see
0xE007 8000, U3RBR - 0xE007 C000 when DLAB = 0, Read Only)”
For details see
0xE007 8008, U3IIR - 0x7008 C008, Read Only)”
(U0THR - 0xE000 C000, U2THR - 0xE007 8000, U3THR - 0xE007 C000 when DLAB = 0, Write Only)”
[1]
Priority Interrupt Type Interrupt Source
-
Highest RX Line Status
Second RX Data
Second Character
Third
Section 16–4.8 “UARTn Line Status Register (U0LSR - 0xE000 C014, U2LSR -
Section 16–4.1 “UARTn Receiver Buffer Register (U0RBR - 0xE000 C000, U2RBR -
Section 16–4.5 “UARTn Interrupt Identification Register (U0IIR - 0xE000 C008, U2IIR -
None
/ Error
Available
Time-out
indication
THRE
Rev. 04 — 26 August 2009
None
OE
Rx data available or trigger level reached
in FIFO (UnFCR0=1)
Minimum of one character in the Rx
FIFO and no character input or removed
during a time period depending on how
many characters are in FIFO and what
the trigger level is set at (3.5 to 4.5
character times).
The exact time will be:
[(word length) × 7 - 2] × 8 + [(trigger level
- number of characters) × 8 + 1] RCLKs
THRE
[2]
or PE
[2]
and
[2]
Section 16–4.2 “UARTn Transmit Holding Register
or FE
[2]
Chapter 16: LPC24XX UART0/2/3
or BI
[2]
UM10237
© NXP B.V. 2009. All rights reserved.
Interrupt Reset
-
UnLSR Read
UnRBR Read
or UARTn FIFO
drops below
trigger level
UnRBR Read
UnIIR Read (if
source of
interrupt) or
THR write
430 of 792
[4]
[2]
[3]
[3]