OM11077 NXP Semiconductors, OM11077 Datasheet - Page 354

• Manufacturer Part Number: OM11077
• Description: MODULE DIMM LPC2478 ARM7
• Manufacturer: NXP Semiconductors

Specifications of OM11077

• Accessory Type: Module Card
• For Use With/related Products: ARM-57TS-LPC2478
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-4742

NXP Semiconductors
Table 329. USB DMA Request Status register (USBDMARSt - address 0xFFE0 C250) bit description
[1]
Table 330. USB DMA Request Clear register (USBDMARClr - address 0xFFE0 C254) bit description
UM10237_4
User manual
Bit
0
1
31:2
Bit
0
1
31:2
Bit
Symbol
Bit
Symbol
DMA can not be enabled for this endpoint and the corresponding bit in the USBDMARSt must be 0.
Symbol
EP0
EP1
EPxx
Symbol
EP0
EP1
EPxx
9.8.2 USB DMA Request Clear register (USBDMARClr - 0xFFE0 C254)
9.8.3 USB DMA Request Set register (USBDMARSet - 0xFFE0 C258)
EP15
EP7
15
7
Value
0
0
0
1
Value
0
0
0
1
Writing one to a bit in this register will clear the corresponding bit in the USBDMARSt
register. Writing zero has no effect.
This register is intended for initialization prior to enabling the DMA for an endpoint. When
the DMA is enabled for an endpoint, hardware clears the corresponding bit in
USBDMARSt on completion of a packet transfer. Therefore, software should not clear the
bit using this register while the endpoint is enabled for DMA operation.
USBDMARClr is a write only register.
The USBDMARClr bit allocation is identical to the USBDMARSt register
Writing one to a bit in this register sets the corresponding bit in the USBDMARSt register.
Writing zero has no effect.
This register allows software to raise a DMA request. This can be useful when switching
from Slave to DMA mode of operation for an endpoint: if a packet to be processed in DMA
mode arrives before the corresponding bit of USBEpIntEn is cleared, the DMA request is
not raised by hardware. Software can then use this register to manually start the DMA
transfer.
EP14
EP6
14
6
Control endpoint OUT (DMA cannot be enabled for this endpoint and EP0
Control endpoint IN (DMA cannot be enabled for this endpoint and EP1 bit
Control endpoint OUT (DMA cannot be enabled for this endpoint and the
Control endpoint IN (DMA cannot be enabled for this endpoint and the EP1
bit must be 0).
Description
bit must be 0).
must be 0).
Endpoint xx (2 ≤ xx ≤ 31) DMA request.
DMA not requested by endpoint xx.
DMA requested by endpoint xx.
Description
EP0 bit must be 0).
Clear the endpoint xx (2 ≤ xx ≤ 31) DMA request.
No effect.
Clear the corresponding bit in USBDMARSt.
EP13
EP5
13
5
Rev. 04 — 26 August 2009
EP12
EP4
12
4
Chapter 13: LPC24XX USB device controller
EP11
EP3
11
3
EP10
EP2
10
2
EP9
EP1
UM10237
9
1
© NXP B.V. 2009. All rights reserved.
(Table
Reset value
0
0
0
Reset value
0
0
0
13–328).
354 of 792
EP8
EP0
8
0