OM11077 NXP Semiconductors, OM11077 Datasheet - Page 36
OM11077
Manufacturer Part Number
OM11077
Description
MODULE DIMM LPC2478 ARM7
Manufacturer
NXP Semiconductors
Specifications of OM11077
Accessory Type
Module Card
For Use With/related Products
ARM-57TS-LPC2478
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
568-4742
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NXP Semiconductors
UM10237_4
User manual
3.3.1.1 Examples of AHB1 settings
3.3.2 AHB Arbiter Configuration register 2 (AHBCFG2 - 0xE01F C18C)
The following examples use the LPC2478 to illustrate how to select the priority of each
AHB1 master based on different system requirements.
Table 31.
Table 32.
Table 33.
[1]
Table 34.
[1]
By default, the AHB2 access is scheduled round-robin (bit 0 = 1). For round-robin
scheduling, the default priority sequence will be Ethernet and CPU.
The AHB2 access priority can be configured as priority scheduling (bit 0 = 0) and priority
of the each of the AHB2 bus masters can be set by writing the priority value (highest
priority = 2, lowest priority = 1).
Bit
14:12
18:16
22:20
26:24
30:28
Bit
14:12
18:16
22:20
26:24
30:28
Bit
14:12
18:16
22:20
26:24
30:28
Bit
14:12
18:16
22:20
26:24
30:28
Sequence based on round-robin.
Sequence based on round-robin.
Symbol
EP1
EP2
EP3
EP4
EP5
Symbol
EP1
EP2
EP3
EP4
EP5
Symbol
EP1
EP2
EP3
EP4
EP5
Symbol
EP1
EP2
EP3
EP4
EP5
Priority sequence (bit 0 = 0): GPDMA, AHB1, CPU, LCD, USB
Priority sequence (bit 0 = 0): USB, LCD, AHB1, CPU, GPDMA
Priority sequence (bit 0 = 0): LCD, CPU, GPDMA, AHB1, USB
Priority sequence (bit 0 = 0): USB, AHB1, CPU, GPDMA, LCD
Description Priority value nnn
CPU
GPDMA
AHB1
USB
LCD
Description Priority value nnn
CPU
GPDMA
AHB1
USB
LCD
Description Priority value nnn
CPU
GPDMA
AHB1
USB
LCD
Description Priority value nnn
GPDMA
USB
LCD
CPU
AHB1
Rev. 04 — 26 August 2009
100 (4)
011 (3)
010 (2)
001 (1)
101 (5)
011 (3)
010 (2)
100 (4)
101 (5)
001 (1)
011 (3)
100 (4)
100 (4)
001 (1)
010 (2)
000
000
011 (3)
001 (1)
010 (2)
Chapter 3: LPC24XX System control
Priority sequence
2
3
4
5
1
Priority sequence
3
4
2
1
5
Priority sequence
3
1
2
5
4
Priority sequence
4
5
1
3
2
[1]
[1]
[1]
[1]
UM10237
© NXP B.V. 2009. All rights reserved.
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