OM11077 NXP Semiconductors, OM11077 Datasheet - Page 487

• Manufacturer Part Number: OM11077
• Description: MODULE DIMM LPC2478 ARM7
• Manufacturer: NXP Semiconductors

Specifications of OM11077

• Accessory Type: Module Card
• For Use With/related Products: ARM-57TS-LPC2478
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-4742

NXP Semiconductors
Table 427. Status Register (CAN1SR - address 0xE004 401C, CAN2SR - address 0xE004 801C) bit description
UM10237_4
User manual
Bit
0
1
2
3
4
Symbol Value
RBS
DOS
TBS1
TCS1
RS
[1]
[2]
0(locked)
1(released)
0(incomplete) The previously requested transmission for Tx Buffer 1 is not complete.
1(complete)
8.7 Error Warning Limit Register (CAN1EWL - 0xE004 4018, CAN2EWL -
8.8 Status Register (CAN1SR - 0xE004 401C, CAN2SR - 0xE004 801C)
0xE004 8018)
This register sets a limit on Tx or Rx errors at which an interrupt can occur. It can be read
at any time but can only be written if the RM bit in CANmod is 1. The default value (after
hardware reset) is 96.
Table 426. Error Warning Limit register (CAN1EWL - address 0xE004 4018, CAN2EWL -
Note that a content change of the Error Warning Limit Register is possible only if the
Reset Mode was entered previously. An Error Status change (Status Register) and an
Error Warning Interrupt forced by the new register content will not occur until the Reset
Mode is cancelled again.
This register contains three status bytes in which the bits not related to transmission are
identical to the corresponding bits in the Global Status Register, while those relating to
transmission reflect the status of each of the 3 Tx Buffers.
Bit Symbol Function
7:0 EWL
Function
Receive Buffer Status. This bit is identical to the RBS bit in the CANxGSR.
Data Overrun Status. This bit is identical to the DOS bit in the CANxGSR.
Transmit Buffer Status 1.
Software cannot access the Tx Buffer 1 nor write to the corresponding
CANxTFI, CANxTID, CANxTDA, and CANxTDB registers because a
message is either waiting for transmission or is in transmitting process.
Software may write a message into the Transmit Buffer 1 and its CANxTFI,
CANxTID, CANxTDA, and CANxTDB registers.
Transmission Complete Status.
The previously requested transmission for Tx Buffer 1 has been successfully
completed.
Receive Status. This bit is identical to the RS bit in the GSR.
address 0xE004 8018) bit description
During CAN operation, this value is compared to both the Tx and
Rx Error Counters. If either of these counter matches this value,
the Error Status (ES) bit in CANSR is set.
Rev. 04 — 26 August 2009
t
t
TSEG1
TSEG2
=
=
Chapter 18: LPC24XX CAN controllers CAN1/2
t
t
SCL
SCL
×
×
(
(
TSEG1
TSEG2
+
+
1
1
)
)
UM10237
© NXP B.V. 2009. All rights reserved.
Reset
Value
96
10
= 0x60 X
0
Reset
Value
0
1
1
1
487 of 792
0
RM
Set
RM
Set
0
1
x
0
(10)
(9)