OM11077 NXP Semiconductors, OM11077 Datasheet - Page 226

• Manufacturer Part Number: OM11077
• Description: MODULE DIMM LPC2478 ARM7
• Manufacturer: NXP Semiconductors

Specifications of OM11077

• Accessory Type: Module Card
• For Use With/related Products: ARM-57TS-LPC2478
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-4742

NXP Semiconductors
Table 198. MII Mgmt Command register (MCMD - address 0xFFE0 0024) bit description
UM10237_4
User manual
Bit
0
1
31:2
Symbol Function
READ
SCAN
-
7.1.12 MII Mgmt Write Data Register (MWTD - 0xFFE0 002C)
7.1.13 MII Mgmt Read Data Register (MRDD - 0xFFE0 0030)
7.1.14 MII Mgmt Indicators Register (MIND - 0xFFE0 0034)
7.1.11 MII Mgmt Address Register (MADR - 0xFFE0 0028)
This bit causes the MII Management hardware to perform a single Read cycle. The Read data is
returned in Register MRDD (MII Mgmt Read Data).
This bit causes the MII Management hardware to perform Read cycles continuously. This is
useful for monitoring Link Fail for example.
Unused
The MII Mgmt Address register (MADR) has an address of 0xFFE0 0028. The bit
definition of this register is shown in
Table 199. MII Mgmt Address register (MADR - address 0xFFE0 0028) bit description
The MII Mgmt Write Data register (MWTD) is a Write Only register with an address of
0xFFE0 002C. The bit definition of this register is shown in
Table 200. MII Mgmt Write Data register (MWTD - address 0xFFE0 002C) bit description
The MII Mgmt Read Data register (MRDD) is a Read Only register with an address of
0xFFE0 0030. The bit definition of this register is shown in
Table 201. MII Mgmt Read Data register (MRDD - address 0xFFE0 0030) bit description
The MII Mgmt Indicators register (MIND) is a Read Only register with an address of
0xFFE0 0034. The bit definition of this register is shown in
Bit
4:0
7:5
12:8
31:13
Bit
15:0
31:16
Bit
15:0
31:16
Symbol
WRITE
DATA
-
Symbol
READ
DATA
-
Symbol
REGISTER
ADDRESS
-
PHY ADDRESS
-
Function
Following an MII Mgmt Read Cycle, the 16 bit data can be read from
this location.
Unused
Function
When written, an MII Mgmt write cycle is performed using the 16 bit
data and the pre-configured PHY and Register addresses from the
MII Mgmt Address register (MADR).
Unused
Rev. 04 — 26 August 2009
Function
This field represents the 5 bit Register Address field of Mgmt
cycles. Up to 32 registers can be accessed.
Unused
This field represents the 5 bit PHY Address field of Mgmt
cycles. Up to 31 PHYs can be addressed (0 is reserved).
Unused
Table
11–199.
Chapter 11: LPC24XX Ethernet
Table
Table
Table
11–201.
11–202.
11–200.
UM10237
© NXP B.V. 2009. All rights reserved.
226 of 792
Reset
value
0x0
0x0
0x0
0x0
Reset
value
0x0
0x0
Reset
value
0
0
0x0
Reset
value
0x0
0x0