OM11077 NXP Semiconductors, OM11077 Datasheet - Page 587
OM11077
Manufacturer Part Number
OM11077
Description
MODULE DIMM LPC2478 ARM7
Manufacturer
NXP Semiconductors
Specifications of OM11077
Accessory Type
Module Card
For Use With/related Products
ARM-57TS-LPC2478
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
568-4742
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NXP Semiconductors
UM10237_4
User manual
9.1 Master Transmitter mode
Table 521. Abbreviations used to describe an I
In Figures
numbers in the circles show the status code held in the I2STAT register. At these points, a
service routine must be executed to continue or complete the serial transfer. These
service routines are not critical since the serial transfer is suspended until the serial
interrupt flag is cleared by software.
When a serial interrupt routine is entered, the status code in I2STAT is used to branch to
the appropriate service routine. For each status code, the required software action and
details of the following serial transfer are given in tables from
Table
In the master transmitter mode, a number of data bytes are transmitted to a slave receiver
(see
initialized as follows:
Table 522. I2CONSET used to initialize Master Transmitter mode
The I
set to logic 1 to enable the I
acknowledge its own slave address or the general call address in the event of another
device becoming master of the bus. In other words, if AA is reset, the I
enter a slave mode. STA, STO, and SI must be reset.
The master transmitter mode may now be entered by setting the STA bit. The I
now test the I
When a START condition is transmitted, the serial interrupt flag (SI) is set, and the status
code in the status register (I2STAT) will be 0x08. This status code is used by the interrupt
service routine to enter the appropriate state service routine that loads I2DAT with the
slave address and the data direction bit (SLA+W). The SI bit in I2CON must then be reset
before the serial transfer can continue.
When the slave address and the direction bit have been transmitted and an
acknowledgment bit has been received, the serial interrupt flag (SI) is set again, and a
number of status codes in I2STAT are possible. There are 0x18, 0x20, or 0x38 for the
master mode and also 0x68, 0x78, or 0xB0 if the slave mode was enabled (AA = logic 1).
The appropriate action to be taken for each of these status codes is detailed in
Table
the master receiver mode by loading I2DAT with SLA+R).
Abbreviation
A
Data
P
Bit
Symbol
Value
Figure
2
22–529.
22–525. After a repeated start condition (state 0x10). The I
C rate must also be configured in the I2SCLL and I2SCLH registers. I2EN must be
120
7
-
-
22–120). Before the master transmitter mode can be entered, I2CON must be
2
C bus and generate a start condition as soon as the bus becomes free.
to 124, circles are used to indicate when the serial interrupt flag is set. The
6
I2EN
1
Rev. 04 — 26 August 2009
Explanation
Not acknowledge bit (high level at SDA)
8 bit data byte
Stop condition
2
C block. If the AA bit is reset, the I
5
STA
0
4
STO
0
Chapter 22: LPC24XX I
2
C operation
3
SI
0
2
AA
x
Table 22–525
2
C block will not
2
C block may switch to
2
C interfaces I
2
UM10237
1
-
-
C interface cannot
© NXP B.V. 2009. All rights reserved.
to
2
C logic will
0
-
-
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2
C0/1/2
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