OM11077 NXP Semiconductors, OM11077 Datasheet - Page 450

• Manufacturer Part Number: OM11077
• Description: MODULE DIMM LPC2478 ARM7
• Manufacturer: NXP Semiconductors

Specifications of OM11077

• Accessory Type: Module Card
• For Use With/related Products: ARM-57TS-LPC2478
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-4742

NXP Semiconductors
UM10237_4
User manual
Table 402. UART1 Interrupt Identification Register (U1IIR - address 0xE001 0008, Read Only)
Bit U1IIR[9:8] are set by the auto-baud function and signal a time-out or end of auto-baud
condition. The auto-baud interrupt conditions are cleared by setting the corresponding
Clear bits in the Auto-baud Control Register.
If the IntStatus bit is 1 no interrupt is pending and the IntId bits will be zero. If the IntStatus
is 0, a non auto-baud interrupt is pending in which case the IntId bits identify the type of
interrupt and handling as described in
interrupt handler routine can determine the cause of the interrupt and how to clear the
active interrupt. The U1IIR must be read in order to clear the interrupt prior to exiting the
Interrupt Service Routine.
The UART1 RLS interrupt (U1IIR[3:1] = 011) is the highest priority interrupt and is set
whenever any one of four error conditions occur on the UART1RX input: overrun error
(OE), parity error (PE), framing error (FE) and break interrupt (BI). The UART1 Rx error
condition that set the interrupt can be observed via U1LSR[4:1]. The interrupt is cleared
upon an U1LSR read.
The UART1 RDA interrupt (U1IIR[3:1] = 010) shares the second level priority with the CTI
interrupt (U1IIR[3:1] = 110). The RDA is activated when the UART1 Rx FIFO reaches the
trigger level defined in U1FCR7:6 and is reset when the UART1 Rx FIFO depth falls below
the trigger level. When the RDA interrupt goes active, the CPU can read a block of data
defined by the trigger level.
The CTI interrupt (U1IIR[3:1] = 110) is a second level interrupt and is set when the UART1
Rx FIFO contains at least one character and no UART1 Rx FIFO activity has occurred in
3.5 to 4.5 character times. Any UART1 Rx FIFO activity (read or write of UART1 RSR) will
clear the interrupt. This interrupt is intended to flush the UART1 RBR after a message has
been received that is not a multiple of the trigger level size. For example, if a peripheral
Bit
3:1
5:4
7:6
8
9
31:10 -
Symbol
IntId
-
FIFO Enable
ABEOInt
ABTOInt
bit description
Value Description
011
010
110
001
000
Rev. 04 — 26 August 2009
Interrupt identification. U1IER[3:1] identifies an interrupt
corresponding to the UART1 Rx FIFO. All other
combinations of U1IER[3:1] not listed above are reserved
(100,101,111).
1 - Receive Line Status (RLS).
2a - Receive Data Available (RDA).
2b - Character Time-out Indicator (CTI).
3 - THRE Interrupt.
4 - Modem Interrupt.
Reserved, user software should not write ones to reserved
bits. The value read from a reserved bit is not defined.
These bits are equivalent to U1FCR[0].
End of auto-baud interrupt. True if auto-baud has finished
successfully and interrupt is enabled.
Auto-baud time-out interrupt. True if auto-baud has timed
out and interrupt is enabled.
Reserved, user software should not write ones to reserved
bits. The value read from a reserved bit is not defined.
Table
17–403. Given the status of U1IIR[3:0], an
Chapter 17: LPC24XX UART1
UM10237
© NXP B.V. 2009. All rights reserved.
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NA
Reset
Value
0
NA
0
0
0