OM11077 NXP Semiconductors, OM11077 Datasheet - Page 563

• Manufacturer Part Number: OM11077
• Description: MODULE DIMM LPC2478 ARM7
• Manufacturer: NXP Semiconductors

Specifications of OM11077

• Accessory Type: Module Card
• For Use With/related Products: ARM-57TS-LPC2478
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-4742

NXP Semiconductors
6. Register description
UM10237_4
User manual
5.3.16 APB interfaces
5.3.17 Interrupt logic
Table 489. Receive FIFO status flags
The APB interface generates the interrupt and DMA requests, and accesses the MCI
adapter registers and the data FIFO. It consists of a data path, register decoder, and
interrupt/DMA logic. DMA is controlled by the General Purpose DMA controller, see that
chapter for details.
The interrupt logic generates an interrupt request signal that is asserted when at least one
of the selected status flags is HIGH. A mask register is provided to allow selection of the
conditions that will generate an interrupt. A status flag generates the interrupt request if a
corresponding mask flag is set.
The MCI registers are shown in
Table 490. Summary of MCI registers
Symbol
RxFifoFull
RxFifoEmpty
RxHalfFull
RxDataAvlbl
RxOverrun
Name
MCIPower
MCIClock
MCIArgument
MMCCommand Command register.
MCIRespCmd
MCIResponse0 Response register.
MCIResponse1 Response register.
MCIResponse2 Response register.
MCIResponse3 Response register.
MCIDataTimer
MCIDataLength Data control register.
MCIDataCtrl
MCIDataCnt
MCIStatus
MCIClear
Description
Power control register.
Clock control register.
Argument register.
Response command register.
Data Timer.
Data control register.
Data counter.
Status register.
Clear register.
Rev. 04 — 26 August 2009
Set to HIGH when the receive FIFO does not contain valid data.
Set to HIGH when an overrun error occurs. This flag is cleared by writing
Description
Set to HIGH when all 16 receive FIFO words contain valid data.
Set to HIGH when 8 or more receive FIFO words contain valid data. This
flag can be used as a DMA request.
Set to HIGH when the receive FIFO is not empty. This flag is the inverse
of the RxFifoEmpty flag.
to the MCIClear register.
Table
21–490.
Chapter 21: LPC24XX SD/MMC card interface
Access Width Reset
R/W
R/W
R/W
R/W
RO
RO
RO
RO
RO
R/W
R/W
R/W
RO
RO
WO
8
12
32
11
6
32
32
32
31
32
16
8
16
22
11
Value
0x00
0x000
0x00000000 0xE008 C008
0x000
0x00
0x00000000 0xE008 C014
0x00000000 0xE008 C018
0x00000000 0xE008 C01C
0x00000000 0xE008 C020
0x00000000 0xE008 C024
0x0000
0x00
0x0000
0x000000
-
[1]
UM10237
© NXP B.V. 2009. All rights reserved.
Address
0xE008 C000
0xE008 C004
0xE008 C00C
0xE008 C010
0xE008 C028
0xE008 C02C
0xE008 C030
0xE008 C034
0xE008 C038
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