OM11077 NXP Semiconductors, OM11077 Datasheet - Page 549

• Manufacturer Part Number: OM11077
• Description: MODULE DIMM LPC2478 ARM7
• Manufacturer: NXP Semiconductors

Specifications of OM11077

• Accessory Type: Module Card
• For Use With/related Products: ARM-57TS-LPC2478
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-4742

NXP Semiconductors
UM10237_4
User manual
6.7 SSPn Raw Interrupt Status Register (SSP0RIS - 0xE006 8018,
6.8 SSPn Masked Interrupt Status Register (SSP0MIS - 0xE006 801C,
Table 476: SSPn Interrupt Mask Set/Clear register (SSP0IMSC - address 0xE006 8014,
SSP1RIS - 0xE003 0018)
This read-only register contains a 1 for each interrupt condition that is asserted,
regardless of whether or not the interrupt is enabled in the SSPnIMSC.
Table 477: SSPn Raw Interrupt Status register (SSP0RIS - address 0xE006 8018, SSP1RIS -
SSP1MIS - 0xE003 001C)
This read-only register contains a 1 for each interrupt condition that is asserted and
enabled in the SSPnIMSC. When an SSP interrupt occurs, the interrupt service routine
should read this register to determine the cause(s) of the interrupt.
Bit
0
1
2
3
7:4
Bit
0
1
2
3
7:4
Symbol
RORIM
RTIM
RXIM
TXIM
-
Symbol
RORRIS
RTRIS
RXRIS
TXRIS
-
SSP1IMSC - 0xE003 0014) bit description
0xE003 0018) bit description
Description
Software should set this bit to enable interrupt when a Receive
Overrun occurs, that is, when the Rx FIFO is full and another frame is
completely received. The ARM spec implies that the preceding frame
data is overwritten by the new frame data when this occurs.
Software should set this bit to enable interrupt when a Receive
Timeout condition occurs. A Receive Timeout occurs when the Rx
FIFO is not empty, and no has not been read for a "timeout period".
Software should set this bit to enable interrupt when the Rx FIFO is at
least half full.
Software should set this bit to enable interrupt when the Tx FIFO is at
least half empty.
Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.
Description
This bit is 1 if another frame was completely received while the
RxFIFO was full. The ARM spec implies that the preceding
frame data is overwritten by the new frame data when this
occurs.
This bit is 1 if the Rx FIFO is not empty, and has not been read
for a "timeout period".
This bit is 1 if the Rx FIFO is at least half full.
This bit is 1 if the Tx FIFO is at least half empty.
Reserved, user software should not write ones to reserved
bits. The value read from a reserved bit is not defined.
Rev. 04 — 26 August 2009
Chapter 20: LPC24XX SSP interface SSP0/1
UM10237
© NXP B.V. 2009. All rights reserved.
Reset Value
0
0
0
1
NA
549 of 792
Reset
Value
0
0
0
0
NA