OM11077 NXP Semiconductors, OM11077 Datasheet - Page 300

• Manufacturer Part Number: OM11077
• Description: MODULE DIMM LPC2478 ARM7
• Manufacturer: NXP Semiconductors

Specifications of OM11077

• Accessory Type: Module Card
• For Use With/related Products: ARM-57TS-LPC2478
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-4742

NXP Semiconductors
Table 258. Color display driven with 2 2/3 pixel data
UM10237_4
User manual
Byte
0
1
2
CLD[7]
P2[Green]
P5[Red]
P7[Blue]
6.10.1 STN displays
6.10.2 TFT displays
6.10 STN and TFT data select
6.11 Interrupt generation
6.8 Panel clock generator
6.9 Timing controller
Each formatter consists of three 3-bit (RGB) shift left registers. RGB pixel data bit values
from the gray scaler are concurrently shifted into the respective registers. When enough
data is available, a byte is constructed by multiplexing the registered data to the correct bit
position to satisfy the RGB data pattern of LCD panel. The byte is transferred to the 3-byte
FIFO, which has enough space to store eight color pixels.
The output of the panel clock generator block is the panel clock, pin LCDDCLK. The panel
clock can be based on either the peripheral clock for the LCD block or the external clock
input for the LCD, pin LCDCLKIN. Whichever source is selected can be divided down in
order to produce the internal LCD clock, LCDCLK.
The panel clock generator can be programmed to output the LCD panel clock in the range
of LCDCLK/2 to LCDCLK/1025 to match the bpp data rate of the LCD panel being used.
The CLKSEL bit in the LCD_POL register determines whether the base clock used is
CCLK or the LCDCLKIN pin.
The primary function of the timing controller block is to generate the horizontal and vertical
timing panel signals. It also provides the panel bias and enable signals. These timings are
all register-programmable.
Support is provided for passive Super Twisted Nematic (STN) and active Thin Film
Transistor (TFT) LCD display types:
STN display panels require algorithmic pixel pattern generation to provide pseudo gray
scaling on monochrome displays, or color creation on color displays.
TFT display panels require the digital color value of each pixel to be applied to the display
data inputs.
Four interrupts are generated by the LCD controller, and a single combined interrupt. The
four interrupts are:
CLD[6]
P2[Red]
P4q[Blue]
P7[Green]
•
•
Master bus error interrupt.
Vertical compare interrupt.
CLD[5]
P1[Blue]
P4[Green]
P7[Red]
Rev. 04 — 26 August 2009
CLD[4]
P1[Green]
P4[Red]
P6[Blue]
CLD[3]
P3[Blue]
P6[Green]
P1[Red]
Chapter 12: LPC24XX LCD controller
CLD[2]
P0[Blue]
P3[Green]
P6[Red]
CLD[1]
P0[Green]
P3[Red]
P5[Blue]
UM10237
© NXP B.V. 2009. All rights reserved.
CLD[0]
P0[Red]
P2[Blue]
P5[Green]
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