OM11077 NXP Semiconductors, OM11077 Datasheet - Page 623
OM11077
Manufacturer Part Number
OM11077
Description
MODULE DIMM LPC2478 ARM7
Manufacturer
NXP Semiconductors
Specifications of OM11077
Accessory Type
Module Card
For Use With/related Products
ARM-57TS-LPC2478
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
568-4742
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UM10237_4
User manual
Table 546. Summary of timer/counter registers
Generic
Name
IR
TCR
TC
PR
PC
MCR
MR0
MR1
MR2
MR3
CCR
Description
Interrupt Register. The IR can be written to
clear interrupts. The IR can be read to
identify which of eight possible interrupt
sources are pending.
Timer Control Register. The TCR is used to
control the Timer Counter functions. The
Timer Counter can be disabled or reset
through the TCR.
Timer Counter. The 32 bit TC is
incremented every PR+1 cycles of PCLK.
The TC is controlled through the TCR.
Prescale Register. The Prescale Counter
(below) is equal to this value, the next clock
increments the TC and clears the PC.
Prescale Counter. The 32 bit PC is a
counter which is incremented to the value
stored in PR. When the value in PR is
reached, the TC is incremented and the PC
is cleared. The PC is observable and
controllable through the bus interface.
Match Control Register. The MCR is used
to control if an interrupt is generated and if
the TC is reset when a Match occurs.
Match Register 0. MR0 can be enabled
through the MCR to reset the TC, stop both
the TC and PC, and/or generate an
interrupt every time MR0 matches the TC.
Match Register 1. See MR0 description.
Match Register 2. See MR0 description.
Match Register 3. See MR0 description.
Capture Control Register. The CCR
controls which edges of the capture inputs
are used to load the Capture Registers and
whether or not an interrupt is generated
when a capture takes place.
Rev. 04 — 26 August 2009
Access Reset
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Chapter 24: LPC24XX Timer0/1/2/3
0
0
0
Value
0
0
0
0
0
0
0
0
[1]
T0MR1 - 0xE000 401C
T0MR2 - 0xE000 4020
T0MR3 - 0xE000 4024
TIMERn Register/
Name & Address
T0IR - 0xE000 4000
T1IR - 0xE000 8000
T2IR - 0xE007 0000
T3IR - 0xE007 4000
T0TCR - 0xE000 4004
T1TCR - 0xE000 8004
T2TCR - 0xE007 0004
T3TCR - 0xE007 4004
T0TC - 0xE000 4008
T1TC - 0xE000 8008
T2TC - 0xE007 0008
T3TC - 0xE007 4008
T0PR - 0xE000 400C
T1PR - 0xE000 800C
T2PR - 0xE007 000C
T3PR - 0xE007 400C
T0PC - 0xE000 4010
T1PC - 0xE000 8010
T2PC - 0xE007 0010
T3PC - 0xE007 4010
T0MCR - 0xE000 4014
T1MCR - 0xE000 8014
T2MCR - 0xE007 0014
T3MCR - 0xE007 4014
T0MR0 - 0xE000 4018
T1MR0 - 0xE000 8018
T2MR0 - 0xE007 0018
T3MR0 - 0xE007 4018
T1MR1 - 0xE000 801C
T2MR1 - 0xE007 001C
T3MR1 - 0xE007 401C
T1MR2 - 0xE000 8020
T2MR2 - 0xE007 0020
T3MR2 - 0xE007 4020
T1MR3 - 0xE000 8024
T2MR3 - 0xE007 0024
T3MR3 - 0xE007 4024
T0CCR - 0xE000 4028
T1CCR - 0xE000 8028
T2CCR - 0xE007 0028
T3CCR - 0xE007 4028
UM10237
© NXP B.V. 2009. All rights reserved.
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