OM11077 NXP Semiconductors, OM11077 Datasheet - Page 723

• Manufacturer Part Number: OM11077
• Description: MODULE DIMM LPC2478 ARM7
• Manufacturer: NXP Semiconductors

Specifications of OM11077

• Accessory Type: Module Card
• For Use With/related Products: ARM-57TS-LPC2478
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-4742

NXP Semiconductors
UM10237_4
User manual
6.1.5 Interrupt Error Clear Register (DMACIntErrClr - 0xFFE0 4010)
6.1.6 Raw Interrupt Terminal Count Status Register (DMACRawIntTCStatus -
6.1.7 Raw Error Interrupt Status Register (DMACRawIntErrorStatus -
Table 656. Interrupt Error Status register (DMACIntErrorStatus - address 0xFFE0 400C) bit
The DMACIntErrClr Register is write-only and clears the error interrupt requests. When
writing to this register, each data bit that is HIGH causes the corresponding bit in the
status register to be cleared. Data bits that are LOW have no effect on the corresponding
bit in the register.
Table 657. Interrupt Error Clear register (DMACIntErrClr - address 0xFFE0 4010) bit
0xFFE0 4014)
The DMACRawIntTCStatus Register is read-only and indicates which DMA channel is
requesting a transfer complete (terminal count interrupt) prior to masking. A HIGH bit
indicates that the terminal count interrupt request is active prior to masking.
shows the bit assignments of the DMACRawIntTCStatus Register.
Table 658. Raw Interrupt Terminal Count Status register (DMACRawIntTCStatus - address
0xFFE0 4018)
The DMACRawIntErrorStatus Register is read-only and indicates which DMA channel is
requesting an error interrupt prior to masking. A HIGH bit indicates that the error interrupt
request is active prior to masking.
the DMACRawIntErrorStatus Register.
Bit
0
1
31:2
Bit
0
1
31:2
Bit
0
1
31:2
Symbol
IntErrorStatus0
IntErrorStatus1
-
Symbol
IntErrClr0
IntErrClr1
-
Symbol
RawIntTCStatus0 Status of the terminal count interrupt for channel 0 prior to
RawIntTCStatus1 Status of the terminal count interrupt for channel 1 prior to
-
description
description
0xFFE0 4014) bit description
Table 32–657
Chapter 32: LPC24XX General Purpose DMA (GPDMA) controller
Rev. 04 — 26 August 2009
Description
Interrupt error status for channel 0.
Interrupt error status for channel 1.
Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.
Description
Writing a 1 clears the error interrupt request for channel 0
(IntErrorStatus0).
Writing a 1 clears the error interrupt request for channel 1
(IntErrorStatus1).
Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.
Description
masking.
masking.
Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.
shows the bit assignments of the DMACIntErrClr Register.
Table 32–659
shows the bit assignments of register of
UM10237
© NXP B.V. 2009. All rights reserved.
Table 32–658
723 of 792
Reset
Value
0x0
0x0
NA
Reset
Value
-
-
NA
Reset
Value
-
-
NA