MPC8313CZQADDC Freescale Semiconductor, MPC8313CZQADDC Datasheet - Page 968

• Manufacturer Part Number: MPC8313CZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO EN EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313CZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Universal Serial Bus Interface
16.3.2.24 SNOOP1 and SNOOP2—Non-EHCI
Note that these registers use big-endian byte ordering and are not defined in the EHCI specification. The
SNOOP1 and SNOOP2 registers provide snooping control and address range selection function.
Transactions that hit a snooping window will generate cache coherent transactions on the internal CSB bus.
When the five lower bits (SNOOPn[27–31]) are equal to 00000, snooping is always disabled on the CSB
for all DMA transfers. When SNOOPn[27–31] is 01011 through 11110, the twenty upper bits
(SNOOPn[0–19]) provide the starting base address for which transactions are snooped. These twenty bits
are compared to the twenty upper bits of the address provided by the DMA block of the USB controller.
When a match occurs, the five lower bits are decoded as shown below. This provides a snooping region of
4 Kbytes to 2 Gbytes within each starting base address that is programmed by the core. The
SNOOPn[20–26] are not used.
16-40
Offset 0x2_3400 (SNOOP1), 0x2_3404 (SNOOP2)
Reset
Bits
3–2
6
5
4
1
0
W
R
0
Name
RXR
RXD
RXT
RXS
RXI
—
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
RX data toggle reset. Whenever a configuration event is received for this endpoint, software must write a one to
this bit in order to synchronize the data PID’s between the Host and device.
RX data toggle inhibit. This bit is only used for test and should always be written as zero. Writing a one to this
bit will cause this endpoint to ignore the data toggle sequence and always accept data packets regardless of
their data PID.
1 PID sequencing enabled
0 PID sequencing disabled
Reserved, should be cleared
RX endpoint type
00 Control
01 Isochronous
10 Bulk
11 Interrupt
Note: When only one endpoint (RX or TX, but not both) of an endpoint pair is used, the unused endpoint should
be configured as a bulk type endpoint.
RX endpoint data sink. This bit should always be written as 0, which selects the dual port memory/DMA engine
as the sink.
RX endpoint stall. This bit will be set automatically upon receipt of a SETUP request if this endpoint is not
configured as a control endpoint. It will be cleared automatically upon receipt a SETUP request if this endpoint
is configured as a control endpoint,
Software can write a one to this bit to force the endpoint to return a STALL handshake to the host. It will continue
to returning STALL until this bit is either cleared by software or automatically cleared as above,
1 Endpoint stalled
0 Endpoint OK
Table 16-32. ENDPTCTRL n Register Field Descriptions (continued)
Figure 16-30. Snoop 1 and Snoop 2 (SNOOP n )
Snoop Address
All zeros
Description
19 20
—
Freescale Semiconductor
26 27
Access: Read/Write
Snoop Enables
31