MPC8313CZQADDC Freescale Semiconductor, MPC8313CZQADDC Datasheet - Page 227

• Manufacturer Part Number: MPC8313CZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO EN EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313CZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

1
whenever an internal unit requests mastership of the coherent system bus (CSB). The SPCR also includes
some other control functions.
Table 5-26
Freescale Semiconductor
Offset 0x00110
Reset
Reset
Default values depend on CFG_RESET_SRC value. See
‘
Bits
4–5
6–7
0
1
2
3
8
W
W
R
R
BUFGTX
BUFGTX125 0 A signal is supplied from an external PHY or oscillator to TSEC1_GTX_CLK125 has the same
BUFMDIO
125
PCIHPE
n
16
0
PCIPR
Name
defines the bit fields of SPCR.
1
OPT
TSEC1588
—
—
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
BUFMDIO —
1 A 2.5 V signal is supplied to TSEC1_GTX_CLK125 from an external PHY or oscillator, and the
1 A 2.5 V signal is supplied from external phy to TSEC1_MDIO.
Reserved. Should be cleared.
bus (CSB) with highest priority, regardless of SPCR[PCIPR] value, when it needs to complete a posted
write transaction from an external PCI master. To follow PCI ordering rules specifications, the PCI
bridge must flush any outstanding write transactions before it can start a new read transaction. Setting
this bit allows faster flushing of the outstanding write transactions coming from the PCI bus onto the
CSB and to the device targets, such as DDR SDRAM and local bus memories.
Reserved. Should be cleared.
00 Level 0 (lowest priority)
01 Level 1
10 Level 2
11 Level 3 (highest priority)
Note: DMA has the same priority as PCI.
Optimize. Setting this bit may enhance the performance of transactions issued to the internal coherent
system bus (CSB) by the security engine (SEC) and the USB controller. Performance is enhanced by
reading more bytes on the bus than actually needed by the master in the case that this is more efficient.
The user may set this bit only if it is known that USB transactions sent to the internal CSB are not
accessing devices in which speculative reads may change the state of the device (for example, FIFOs
in which reading a byte may advance some internal counter).
0 No performance enhancement.
1 Performance enhancement by speculative reading is enabled.
0 A 3.3 V signal is supplied from external phy to TSEC1_MDIO.
PCI highest priority enable. If this bit is set, the PCI bridge is permitted to request the coherent system
PCI bridge CSB request priority. The level of priority can be chosen from 4 possible levels.
n
17
1
voltage level as the LVddb power supply.
LVdbb power supply has a 3.3 V voltage level.
Figure 5-13. System Priority Configuration Register (SPCR)
18
0
2
TSECDP
PCIHPE
19
0
3
Table 5-26. SPCR Bit Settings
20
TSECBDP
0
4
—
Table
21
0
5
All zeros
5-27.
TSECEP
22
6
0
Description
PCIPR
23
0
7
OPT
24
8
0
TBEN
25
0
9
COREPR
10
26
0
—
11
27
0
System Configuration
Access: Read/Write
12
28
0
29
0
—
30
0
5-19
15
31
0