MPC8313CZQADDC Freescale Semiconductor, MPC8313CZQADDC Datasheet - Page 317
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MPC8313CZQADDC
Manufacturer Part Number
MPC8313CZQADDC
Description
Microprocessors - MPU 8313 REV2.2 PB NO EN EXT
Manufacturer
Freescale Semiconductor
Datasheet
1.MPC8313CZQADDC.pdf
(1214 pages)
Specifications of MPC8313CZQADDC
Processor Series
MPC8313
Core
e300
Data Bus Width
16 bit
Maximum Clock Frequency
133 MHz
Program Memory Size
16 KB
Data Ram Size
16 KB
Interface Type
I2C
Mounting Style
SMD/SMT
Package / Case
PBGA
Number Of Programmable I/os
32
Number Of Timers
4
Available stocks
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Manufacturer
Quantity
Price
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Part Number:
MPC8313CZQADDC
Manufacturer:
Freescale Semiconductor
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10 000
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The transaction with an address only transfer type, the arbiter performs as follows:
6.3.2.5
Table 6-11
The transaction with a reserved transfer type, the arbiter performs as follows:
6.3.2.6
Table 6-12
The transaction with an illegal (eciwx, ecowx) transfer type, the arbiter performs as follows:
Freescale Semiconductor
1. Ends the address tenure by asserting AACK.
2. Reports on the event to AER[AO].
3. Issues reset request, MCP or regular interrupt according to AERR[AO] and AIDR[AO] if enabled
4. Updates transaction attributes and address of AEATR and AEADR for the first error event.
1. Ends the address tenure by asserting AACK.
2. Reports on the event to AER[RES].
3. Issues reset request, MCP or regular interrupt according to AERR[RES] and AIDR[RES], if
4. Updates transaction attributes and address of AEATR and AEADR for the first error event.
1. Ends the address tenure by asserting AACK.
2. Starts data tenure and ends data tenure by asserting TEA.
3. Reports on the event in AER[ECW].
4. Issues reset request, MCP or regular interrupt according to AERR[ECW] and AIDR[ECW], if
5. Updates transaction attributes and address of AEATR and AEADR for the first error event.
by AMR[AO].
enabled by AMR[RES].
enabled by AMR[ECW].
shows transaction types defined as reserved.
shows transaction types defined as illegal.
Reserved Transaction Type
Illegal (eciwx/ecowx) Transaction Type
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
10100
11100
Table 6-11. Reserved Transaction Type Encoding
Table 6-12. Illegal Transaction Type Encoding
ttype[0:4]
ttype[0:4]
00101
10110
00011
00111
01111
1xx01
1xx11
External control word write (ecowx)
External control word read (eciwx)
Reserved
Reserved for customer
Reserved
Reserved
Reserved
Reserved
Reserved for customer
Bus Commands
Bus command
Arbiter and Bus Monitor
6-15
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