MPC8313CZQADDC Freescale Semiconductor, MPC8313CZQADDC Datasheet - Page 649

• Manufacturer Part Number: MPC8313CZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO EN EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313CZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

exception that a ‘done’ field is set. The second is a status field writeback. That status field writeback occurs
to report the result of ICV checking if ICV check writeback is enabled.
Many security protocols involve both encryption and hashing of packet payloads. To accomplish this
without requiring two passes through the data, the channel can configure data flows through more than one
EU. In such cases, one EU is designated the primary EU, and the other as the secondary EU. The primary
EU receives its data from memory through the controller, and the secondary EU receives its data by
‘snooping’ SEC buses.
There are two types of snooping:
In the SEC the secondary EU is always the MDEU.
For more information, refer to
14.1.4
The SEC controller manages on-chip resources, including the individual execution units (EUs), FIFOs, the
master/slave interface to the MPC8313E system bus, and the internal buses that connect all the various
modules. The controller receives service requests from the master/slave interface and from the channel,
and schedules the required activities. The controller provides for two ways of operating the execution
units:
The system bus interface and access to system memory are critical factors in performance, and the 64-bit
master/slave interface of the SEC controller allows it to achieve performance unattainable on secondary
buses.
14.1.4.1
Processing begins when a descriptor pointer is written to the fetch FIFO of the channel. Based on the
services requested by the descriptor header, the channel asks the controller to assign the necessary EUs to
the channel. Once the required EU has been reserved, the channel requests that the controller fetch and
load the appropriate data. The controller acts as a master on the system bus, reading and writing on byte
boundaries. The channel operates the EU, and makes further requests to the controller to write output data
to system memory. When the descriptor processing is complete, the channel asks the controller to release
the EU.
Freescale Semiconductor
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Input data can be fed to the primary EU and the same input data snooped by the secondary EU.
This is called ‘in-snooping.’
Output data from the primary EU can be snooped by the secondary EU. This is called
‘out-snooping.’
Channel-controlled access—The channel can request a particular service from any available
execution unit. This is the normal operating condition.
Host-controlled access—The host can move data into and out of any execution unit directly
through memory-mapped EU registers. This is typically only used for debug.
SEC Controller
Channel-Controlled Access
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Section 14.5, “Channel."
Security Engine (SEC) 2.2
14-7