MPC8313CZQADDC Freescale Semiconductor, MPC8313CZQADDC Datasheet - Page 7
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MPC8313CZQADDC
Manufacturer Part Number
MPC8313CZQADDC
Description
Microprocessors - MPU 8313 REV2.2 PB NO EN EXT
Manufacturer
Freescale Semiconductor
Datasheet
1.MPC8313CZQADDC.pdf
(1214 pages)
Specifications of MPC8313CZQADDC
Processor Series
MPC8313
Core
e300
Data Bus Width
16 bit
Maximum Clock Frequency
133 MHz
Program Memory Size
16 KB
Data Ram Size
16 KB
Interface Type
I2C
Mounting Style
SMD/SMT
Package / Case
PBGA
Number Of Programmable I/os
32
Number Of Timers
4
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MPC8313CZQADDC
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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Paragraph
Number
5.3.2.4
5.3.2.5
5.3.2.6
5.3.2.7
5.3.2.7.1
5.3.2.7.2
5.3.2.8
5.3.2.9
5.4
5.4.1
5.4.2
5.4.3
5.4.4
5.4.4.1
5.4.4.2
5.4.4.3
5.4.5
5.4.5.1
5.4.5.2
5.4.6
5.4.6.1
5.5
5.5.1
5.5.2
5.5.3
5.5.4
5.5.5
5.5.5.1
5.5.5.2
5.5.5.3
5.5.5.4
5.5.5.5
5.5.5.6
5.5.6
5.5.6.1
5.5.6.2
5.5.7
5.6
5.6.1
5.6.2
5.6.3
Freescale Semiconductor
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Software Watchdog Timer (WDT)................................................................................. 5-29
Real Time Clock Module (RTC).................................................................................... 5-35
Periodic Interval Timer (PIT) ........................................................................................ 5-42
WDT Overview.......................................................................................................... 5-29
WDT Features............................................................................................................ 5-29
WDT Modes of Operation ......................................................................................... 5-30
WDT Memory Map/Register Definition ................................................................... 5-30
Functional Description............................................................................................... 5-33
Initialization/Application Information ....................................................................... 5-35
RTC Overview ........................................................................................................... 5-35
RTC Features ............................................................................................................. 5-36
RTC Modes of Operation........................................................................................... 5-36
RTC External Signal Description .............................................................................. 5-36
RTC Memory Map/Register Definition ..................................................................... 5-37
Functional Description............................................................................................... 5-41
RTC Programming Guidelines................................................................................... 5-42
PIT Overview............................................................................................................. 5-42
PIT Features............................................................................................................... 5-43
PIT Modes of Operation ............................................................................................ 5-43
System Priority and Configuration Register (SPCR) ............................................ 5-18
System I/O Configuration Register Low (SICRL) ................................................ 5-20
System I/O Configuration Register High (SICRH) ............................................... 5-23
Debug Configuration ............................................................................................. 5-26
DDR Control Driver Register (DDRCDR)............................................................ 5-27
DDR Debug Status Register (DDRDSR) .............................................................. 5-28
System Watchdog Control Register (SWCRR) ..................................................... 5-31
System Watchdog Count Register (SWCNR) ....................................................... 5-32
System Watchdog Service Register (SWSRR)...................................................... 5-32
Software Watchdog Timer Unit ............................................................................. 5-33
Modes of Operation ............................................................................................... 5-34
WDT Programming Guidelines............................................................................. 5-35
Real Time Counter Control Register (RTCNR) .................................................... 5-37
Real Time Counter Load Register (RTLDR)......................................................... 5-38
Real Time Counter Prescale Register (RTPSR) .................................................... 5-39
Real Time Counter Register (RTCTR) .................................................................. 5-39
Real Time Counter Event Register (RTEVR)........................................................ 5-40
Real Time Counter Alarm Register (RTALR) ....................................................... 5-40
Real Time Counter Unit......................................................................................... 5-41
RTC Operational Modes ........................................................................................ 5-41
DDR Debug Configuration................................................................................ 5-26
Local Bus Debug Configuration........................................................................ 5-27
Contents
Title
Number
Page
vii
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