MPC8313CZQADDC Freescale Semiconductor, MPC8313CZQADDC Datasheet - Page 597

• Manufacturer Part Number: MPC8313CZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO EN EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313CZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Figure 13-4
Table 13-7
13.3.1.3
Reading this register generates an interrupt acknowledge transaction on the PCI bus. The value that is read
is undefined.
13.3.2
This section describes the control and status registers.
13.3.2.1
The PCI error status register (PCI_ESR) contains status bits for various types of error conditions captured
by the PCI controller. Each status bit is set when the corresponding error condition is captured. PCI_ESR
is a write-1-to-clear type register. A bit is cleared whenever the register is written and the data in the
corresponding bit location is a 1.
Freescale Semiconductor
Offset 0x00
Reset
Offset 0x4
Reset
31–0
Bits
W
R MERR
W
R
31
w1c
0
shows the bit settings of the PCI_CONFIG_DATA register.
PCI Memory-Mapped Control and Status Registers
CFG_DATA Configuration data. This field contains the data transferred on a PCI configuration transaction.
shows the PCI_CONFIG_DATA register fields.
1
PCI Interrupt Acknowledge Register (PCI_INT_ACK)
PCI Error Status Register (PCI_ESR)
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Name
Table 13-7. PCI_CONFIG_DATA Field Descriptions
Figure 13-5. PCI Error Status Register (PCI_ESR)
—
Figure 13-5
Figure 13-4. PCI_CONFIG_DATA
shows the PCI_ESR fields.
20
APAR PCISERR MPERR TPERR NORSP TABT
w1c
21
CFG_DATA
All zeros
All zeros
w1c
22
Description
w1c
23
w1c
24
w1c
25
Access: Read/Write
w1c
26
PCI Bus Interface
Access: w1c
27
—
13-15
0
31