MPC8313CZQADDC Freescale Semiconductor, MPC8313CZQADDC Datasheet - Page 1163

• Manufacturer Part Number: MPC8313CZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO EN EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313CZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

5.3.2.7.1, 5-26
5.3.2.8, 5-27
5.7.2, 5-50
5.7.6.1, 5-62
5.8.1, 5-65
5.8.3.2, 5-67
5.8.3.4, 5-70
5.8.3.7.1, 5-79
5.8.3.7.2, 5-84
5.8.3.7.3, 5-88
Freescale Semiconductor
31
PMCI
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Power management controller interrupt.
When set, indicates that one of the following events has occurred:
If PMCMR[PMCIE] is set, the PMC interrupt request to the PowerPC core is driven, causing the PowerPC
core to exit its low power state. PMCI can be cleared by writing a 1 to it (writing zero has no effect).
• One of the unmasked wake-up events (bits 23–30) occurred and PMCCR1[PME_vPEN] is cleared, or
• PM current state (as indicated in PMCCR1[CURR_STATE]) is different than PM next state (as written to
• CSB platform is in low power mode and a new CSB bus request is detected
PCIPMR1[Power_State] and indicated in PMCCR1[NEXT_STATE]) and PMCCR1[USE_STATE] is set,
or
Rewrote the first paragraph as follows:
The DDR debug configuration enables a DDR memory controller to enter debug
mode in which the DDR SDRAM source ID field and data valid strobe are driven
onto one oftwo optional sets of pins:
In Table 5-30, added the following note in the Description column for DDR_cfg:
Note: DDR_cfg must be set according to the logical type of the DDR memory devices, as it effects
Changed the 5th thru 8th bullets to read:
• Maximum period of ~412.3 seconds (at 167-MHz bus clock and prescaler =
• Maximum period of ~825 seconds (at 167-MHz bus clock and prescaler = 256)
• Maximum period of thousands of years (at 167-MHz bus clock and prescaler =
• 3-nanosecond timer resolution (at 167-MHz bus clock and no prescaler)
• Resolution and maximum period can be traded off by selecting prescaler
In the third paragreaph, changed the last sentence to read:
The maximum period (when the reference value is all ones and the prescaler
divides by 256) for one 16-bit timer is ~50 ms at 333 MHz.
Deleted the section number and title only and renumbered the remaining sections.
In Table 5-67, bits 23–30, added the following footnote to each bit description:
Note: This bit will not be affected by the wake-up event if the corresponding mask bit in PMCMR
Table 5-67, bit 31, changed the description to the following:
In Figure 5-54, changed the bit field ‘NEXT_STATE’ to read only.
In the text box of Figure 5-57, changed ‘Uninitialized’ to ‘Not Initialized’.
In note 6, changed the Word ‘uninitialized’ to ‘non-initialized’.
In the Notes, changed the second note 3 to 4 and renumbered the rest of the notes.
Added the initial two steps.
In Figure 5-58, changed the signal name ‘PWR_EN’ to ‘EXT_PWR_CTRL’.
In Figure 5-59, changed the signal name ‘PWR_EN’ to ‘EXT_PWR_CTRL’.
256) for 16-bit timer
for 32-bit timer
256) for 64-bit timer
divisor
logic behavior of the DDR controller as well as the physical parameters of the DDR I/O pads.
is cleared.
Revision History
A-5