MPC8313CZQADDC Freescale Semiconductor, MPC8313CZQADDC Datasheet - Page 401

• Manufacturer Part Number: MPC8313CZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO EN EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313CZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

9.3.2.2
Table 9-4
Freescale Semiconductor
MODT[0:1]
MDM[0:3]
MCS[0:1]
Signal
MCK,
MCK
Signal
MWE
contains the detailed descriptions of the clock signals of the DDR controller.
Clock Interface Signals
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Table 9-3. Memory Interface Signals—Detailed Signal Descriptions (continued)
I/O
O
I/O
O
O
O
O
DRAM clock output and its complement. See
Meaning
Chip selects. Two chip selects supported by the memory controller.
Write enable. Asserted when a write transaction is issued to the SDRAM. This is also used for mode
registers set commands and precharge commands.
DDR SDRAM data output mask. Masks unwanted bytes of data transferred during a write. They are
needed to support sub-burst-size transactions (such as single-byte writes) on SDRAM where all I/O
occurs in multi-byte bursts. MDM0 corresponds to the most significant byte (MSB).
byte lane encodings.
On-Die termination. Memory controller outputs for the ODT to the DRAM. MODT[0:1] represents the
on-die termination for the associated data, data masks, and data strobes.
Timing Assertion/Negation—Timing is controlled by the DDR_CLK_CNTL register at offset 0x130.
Meaning
Meaning
Meaning
Meaning
Timing Assertion/Negation—Asserted to signal any new transaction to the SDRAM. The transaction
Timing Assertion/Negation—Similar timing as MRAS and MCAS. Used for write commands.
Timing Assertion/Negation—Same timing as MDQx as outputs.
Timing Assertion/Negation—Driven in accordance with JEDEC DRAM specifications for on-die
State
State
State
State
State
Table 9-4. Clock Signals—Detailed Signal Descriptions
Asserted/Negated—The JEDEC DDR SDRAM specifications require true and complement
Asserted—Selects a physical SDRAM bank to perform a memory operation as described in
Negated—Indicates no SDRAM action during the current cycle.
High impedance—Always driven unless the memory controller is disabled.
Asserted—Indicates a memory write operation. See
Negated—Indicates a memory read operation.
High impedance—MWE is always driven unless the memory controller is disabled.
Asserted—Prevents writing to DDR SDRAM. Asserted when data is written to DRAM if the
Negated—Allows the corresponding byte to be read from or written to the SDRAM.
High-impedance—Always driven unless the memory controller is disabled.
Asserted/Negated—Represents the ODT driven by the DDR memory controller.
High impedance—Always driven.
clocks. A clock edge is seen by the SDRAM when the true and complement cross.
Section 9.4.1.1, “Chip Select Memory Bounds (CSn_BNDS),”
“Chip Select Configuration (CSn_CONFIG).”
MCS[0:1] signals to begin a memory cycle.
must adhere to the timing constraints set in TIMING_CFG_0–TIMING_CFG_3.
states required on MWE for various other SDRAM commands.
corresponding byte(s) should be masked for the write. Note that the MDM n signals are
active-high for the DDR controller. MDM n is part of the DDR command encoding.
termination timings. It is configured through the CS n _CONFIG[ODT_RD_CFG] and
CS n _CONFIG[ODT_WR_CFG] fields.
Section 9.5.4.1, “Clock Distribution.”
Description
Description
The DDR controller asserts one of the
Table 9-30
for more information on the
and
DDR Memory Controller
Section 9.4.1.2,
Table 9-24
shows
9-7