MPC8313CZQADDC Freescale Semiconductor, MPC8313CZQADDC Datasheet - Page 533

• Manufacturer Part Number: MPC8313CZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO EN EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313CZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

MxMR[AM] = 000
MxMR[AM] = 001
MxMR[AM] = 010
MxMR[AM] = 011
MxMR[AM] = 100
MxMR[AM] = 101
MxMR[AM] = 110
MxMR[AM] = 111
Table 10-42
column address multiplexing on the LA[10:25] signals.
Note that any change to the AMX field from one RAM word to the next RAM word executed results in an
address phase on the {LAD
in the OR
during the LALE phase.
10.4.4.4.8
When a read access is handled by the UPM, and the UTA bit is 1 (data is to be sampled by the eLBC), the
value of the DLT3 bit in the same RAM word, in conjunction with M
data input is sampled by the eLBC as follows:
Freescale Semiconductor
AMX = 10
AMX = 00
AMX = 10
AMX = 00
AMX = 10
AMX = 00
AMX = 10
AMX = 00
AMX = 10
AMX = 00
AMX = 10
AMX = 00
AMX = 10
AMX = 10
(Row)
(Row)
(Row)
(Row)
(Row)
(Row)
(Col)
(Col)
(Col)
(Col)
(Col)
(Col)
n
and LCRR registers. The LGPL[0:5] signals maintain the value specified in the RAM word
msb
shows how the RAM word AMX bits and M
0
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
AMX must not change values in any RAM word which begins a loop.
Data Valid and Data Sample Control (UTA)
1
2
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
3
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
4
n
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
5
, LA
LAD
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
6
LAD
n
Table 10-42. UPM Address Multiplexing
10 11 12 13 14 15 16 17 18 19 20 21 22 23
7
} bus with the assertion of LALE for the number of cycles set for LALE
LAD
10 11 12 13 14 15 16 17 18 19 20 21 22
8
LAD
9
LAD
10 11 12 13 14 15 16 17 18 19 20
LAD
NOTE
Internal Transaction Address
LA
LA
Reserved
Reserved
x
LA
MR[AM] settings can be used to affect row ×
LA
LA
LA
13 14
x
MR[GPL4], determines when the
14
LAD
LAD
LAD
21
23
24
25
15
15
15
22 23 24 25 26 27 28 29 30
24 25
25
16 17 18 19 20 21 22 23 24
16 17 18 19 20 21 22 23 24
16 17 18 19 20 21 22 23 24
16 17 18 19 20 21 22 23 24
Enhanced Local Bus Controller
17 18 19 20 21 22 23 24
18 19 20 21 22 23 24
LA
LA
LA
LA
LA
LA
10-85
lsb
31
25
25
25
25
25
25