MPC8313CZQADDC Freescale Semiconductor, MPC8313CZQADDC Datasheet - Page 59

• Manufacturer Part Number: MPC8313CZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO EN EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313CZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Table
Number
8-23
8-24
8-25
8-26
8-27
8-28
8-29
8-30
8-31
9-1
9-2
9-3
9-4
9-5
9-6
9-7
9-8
9-9
9-10
9-11
9-12
9-13
9-14
9-15
9-16
9-17
9-18
9-19
9-20
9-21
9-22
9-23
9-24
9-25
9-26
9-27
9-28
9-29
9-30
9-31
Freescale Semiconductor
SERMR Field Descriptions................................................................................................... 8-24
SERCR Field Descriptions.................................................................................................... 8-24
SIFCR_H Field Descriptions ................................................................................................ 8-25
SIFCR_L Field Descriptions................................................................................................. 8-25
SEFCR Field Descriptions .................................................................................................... 8-26
SERFR Field Descriptions .................................................................................................... 8-27
SCVCR Field Descriptions ................................................................................................... 8-27
SMVCR Field Descriptions .................................................................................................. 8-28
7Interrupt Source Priority Levels.......................................................................................... 8-31
DDR Memory Interface Signal Summary .............................................................................. 9-3
Memory Address Signal Mappings......................................................................................... 9-4
Memory Interface Signals—Detailed Signal Descriptions ..................................................... 9-5
Clock Signals—Detailed Signal Descriptions ........................................................................ 9-7
DDR Memory Controller Memory Map................................................................................. 9-8
CSn_BNDS Field Descriptions............................................................................................. 9-10
CSn_CONFIG Field Descriptions ........................................................................................ 9-10
TIMING_CFG_3 Field Descriptions .................................................................................... 9-12
TIMING_CFG_0 Field Descriptions .................................................................................... 9-13
TIMING_CFG_1 Field Descriptions .................................................................................... 9-14
TIMING_CFG_2 Field Descriptions .................................................................................... 9-17
DDR_SDRAM_CFG Field Descriptions.............................................................................. 9-19
DDR_SDRAM_CFG_2 Field Descriptions.......................................................................... 9-21
DDR_SDRAM_MODE Field Descriptions.......................................................................... 9-23
DDR_SDRAM_MODE_2 Field Descriptions...................................................................... 9-23
DDR_SDRAM_MD_CNTL Field Descriptions................................................................... 9-24
Settings of DDR_SDRAM_MD_CNTL Fields .................................................................... 9-25
DDR_SDRAM_INTERVAL Field Descriptions .................................................................. 9-26
DDR_DATA_INIT Field Descriptions ................................................................................. 9-27
DDR_SDRAM_CLK_CNTL Field Descriptions ................................................................. 9-27
DDR_INIT_ADDR Field Descriptions ................................................................................ 9-28
DDR_IP_REV1 Field Descriptions ...................................................................................... 9-28
DDR_IP_REV2 Field Descriptions ...................................................................................... 9-29
Byte Lane to Data Relationship ............................................................................................ 9-33
Supported DDR1 SDRAM Device Configurations .............................................................. 9-33
Supported DDR2 SDRAM Device Configurations .............................................................. 9-34
DDR1 Address Multiplexing for 32-Bit Data Bus with Interleaving Disabled .................... 9-35
DDR2 Address Multiplexing ................................................................................................ 9-36
Example of Address Multiplexing for 32-Bit Data Bus Interleaving Between
DDR SDRAM Command Table............................................................................................ 9-38
DDR SDRAM Interface Timing Intervals ............................................................................ 9-39
Two Banks with Partial Array Self Refresh Disabled...................................................... 9-36
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
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