MPC8313CZQADDC Freescale Semiconductor, MPC8313CZQADDC Datasheet - Page 1166

• Manufacturer Part Number: MPC8313CZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO EN EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313CZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Revision History
10.3.1.15, 10-33
10.3.1.16, 10-33
10.4.2, 10-45
10.4.2.1, 10-46
A-8
TRLX
Option Register Attributes
0
0
0
0
0
0
0
0
0
0
0
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
EHTR
0
0
0
0
0
0
1
1
1
1
1
eLBC in GPCM
Mode
In Table 10-22, for bit 0, changed the first sentence in the Description column to
read:
This bit should be set when using low bus clock frequencies (see device hardware
specifications for applicable frequencies).
In Table 10-22, for bits 27-31, changed the first paragraph to the following:
System clock divider. Sets the frequency ratio between the system clock and the
local bus clock. The system clock is equivalent to csb_clk or twice csb_clk (if
RCWL[LBIUCM] is set). Only the values shown below are allowed.
In Table 10-23, bits 16–19, changed the first sentence to read: ‘... high (CW0,
CW1, RBW and RSW), FCM ...’.
Replaced Figure 10-31 with the following:
Replaced Table 10-30 with the following:
XACS
0
0
0
1
1
1
0
0
0
1
1
LAD[0:7]
LA[6:25]
LWE0
LCS n
ACS
LOE
0X
0X
0X
0X
10
11
10
11
10
11
10
t
ARCS
(½)
(½)
¼
½
¼
½
0
0
1
2
0
0
1
Signal Timing (LCLK Clock Cycles)
(1½+SCY)
1¾+SCY
1½+SCY
1¾+SCY
1½+SCY
(2+SCY)
2+SCY
2+SCY
1+SCY
1+SCY
2+SCY
2+SCY
1+SCY
t
CSRP
t
CE
OE
WE
Data[7:0]
A[19:0]
AOE
1
1
1
1
1
2
1
1
1
1
1
Memory/Peripheral
t
OEN
0
0
0
0
0
0
1
1
1
1
1
1
Freescale Semiconductor
2+SCY
2+SCY
2+SCY
2+SCY
2+SCY
3+SCY
3+SCY
3+SCY
3+SCY
3+SCY
3+SCY
t
RC