MPC8313CZQADDC Freescale Semiconductor, MPC8313CZQADDC Datasheet - Page 569

• Manufacturer Part Number: MPC8313CZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO EN EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313CZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

12.3.8
Each DMA channel has a set of seven 32-bit registers (mode, status, current descriptor address, next
descriptor address, source address, destination address, and byte count) to support transactions. The
following sections describe the format of the DMA support registers.
12.3.8.1
This section describes the DMA mode register. The mode register allows software to start the DMA
transfer and to control various DMA transfer characteristics.
Table 12-10
Freescale Semiconductor
Offset: 0x100, 0x180, 0x200, 0x280
Reset
Reset
31–24
23–21
Bits
Bits
1
0
W
W
R
R
31
15
SAHTS
Name
IM1IM
IM0IM
Name
BWC
—
DMA Registers
describes the DMAMRn register.
DMA Mode Register (DMAMR n )
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
14
Inbound message 1 interrupt mask.
0 Inbound message 1 interrupt is allowed
1 Inbound message 1 interrupt is masked. IMISR[IM1I] is cleared
Inbound message 0 interrupt mask.
0 Inbound message 0 interrupt is allowed
1 Inbound message 0 interrupt is masked. IMISR[IM0I] is cleared
Reserved
Bandwidth control. Only applies when multiple channels are executing transfers concurrently. The field
determines how many cache lines a given channel is allowed to transfer after it is granted access to the IOS
interface and before it releases the interface to the next channel. This allows the user to prioritize the DMA
channels. The BWC values are listed as follows:
000 1 cache line
001 2 cache lines
010 4 cache lines
011 8 cache lines
100 16 cache lines
Others Reserved
DAHE SAHE
13
12
Table 12-9. IMIMR Field Descriptions (continued)
—
Figure 12-10. DMA Mode Register (DMAMR n )
11
Table 12-10. DMAMR n Field Descriptions
PRC
10
9
—
24
8
All zeros
All zeros
EOTIE
Description
Description
23
7
BWC
Figure 12-10
6
21
—
DMSEN IRQS
shows the DMAMRn fields.
20
4
TEM
19
3
Access: User read/write
CTM
DMA/Messaging Unit
—
18
2
CC
17
1
DAHTS
CS
12-9
16
0