MPC8313CZQADDC Freescale Semiconductor, MPC8313CZQADDC Datasheet - Page 946

• Manufacturer Part Number: MPC8313CZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO EN EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313CZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Universal Serial Bus Interface
16.3.2.4
In host mode, this register is used by the controller to index the periodic frame list. The register updates
every 125 microseconds (once each microframe). Bits N–3 are used to select a particular entry in the
periodic frame list during periodic schedule execution. The number of bits used for the index depends on
the size of the frame list as set by system software in USBCMD[FS].
This register must be written as a DWord. Byte writes produce-undefined results. This register cannot be
written unless the USB DR controller is in the Halted state as indicated by the USBSTS[HCH]. A write to
this register while USBCMD[RS] is set produces undefined results. Writes to this register also affect the
SOF value.
In device mode, this register is read-only and, the USB DR controller updates the FRINDEX[13–3]
register from the frame number indicated by the SOF marker. Whenever a SOF is received by the USB
bus, FRINDEX[13–3] is checked against the SOF marker. If FRINDEX[13–3] is different from the SOF
marker, FRINDEX[13–3] is set to the SOF value and FRINDEX[2–0] is cleared (that is, SOF for 1 msec
frame). If FRINDEX[13–3] is equal to the SOF value, FRINDEX[2–0] is incremented (that is, SOF for
125-µsec microframe.)
16-18
Bits
4
3
2
1
0
Name
SEE
PCE
UEE
FRE
UE
Frame Index Register (FRINDEX)
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
System error enable. When this bit is a one, and USBSTS[SEI] is a one, the controller will issue an interrupt.
The interrupt is acknowledged by software clearing USBSTS[SEI].
0 Disable
1 Enable
Frame list rollover enable. When this bit is a one, and USBSTS[FRI] is a one, the controller will issue an
interrupt. The interrupt is acknowledged by software clearing USBSTS[FRI]. Only used by the host mode.
0 Disable
1 Enable
Port change detect enable. When this bit is a one, and USBSTS[PCI] is a one, the controller will issue an
interrupt. The interrupt is acknowledged by software clearing USBSTS[PCI].
0 Disable
1 Enable
USB error interrupt enable. When this bit is a one, and USBSTS[UEI] is a one, the controller will issue an
interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing USBSTS[UEI].
0 Disable
1 Enable
USB interrupt enable. When this bit is a one, and USBSTS[UI] is a one, the DR controller will issue an
interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing USBSTS[UI].
0 Disable
1 Enable
Table 16-12. USBINTR Register Field Descriptions (continued)
Description
Freescale Semiconductor