MPC8313CZQADDC Freescale Semiconductor, MPC8313CZQADDC Datasheet - Page 862
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MPC8313CZQADDC
Manufacturer Part Number
MPC8313CZQADDC
Description
Microprocessors - MPU 8313 REV2.2 PB NO EN EXT
Manufacturer
Freescale Semiconductor
Datasheet
1.MPC8313CZQADDC.pdf
(1214 pages)
Specifications of MPC8313CZQADDC
Processor Series
MPC8313
Core
e300
Data Bus Width
16 bit
Maximum Clock Frequency
133 MHz
Program Memory Size
16 KB
Data Ram Size
16 KB
Interface Type
I2C
Mounting Style
SMD/SMT
Package / Case
PBGA
Number Of Programmable I/os
32
Number Of Timers
4
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Enhanced Three-Speed Ethernet Controllers
15.6.2.1.1
A hard reset occurs when the system powers up. All eTSEC’s registers and control logic are reset to their
default states after a hard reset has occurred. In this state, each eTSEC behaves like a PowerQUICC II Pro
device, except for the absence of out-of-sequence TxBD features. That is, initially TCP/IP off-load is
disabled and only single RxBD and TxBD rings are accessible.
15.6.2.1.2
After the system has undergone a hard reset, software must initialize certain basic eTSEC registers. Other
registers can also be initialized during this time, but they are optional and must be determined based on the
requirements of the system. See
for register initialization.
After the initialization of registers is performed, the user must execute the following steps in the order
described below to bring the eTSEC into a functional state (out of reset):
15-144
1. Write to the MACCFG1 register and set the appropriate bits. These need to include RX_EN and
2. For the transmission of Ethernet frames, TxBDs must first be built in memory, linked together as
3. Likewise, for the reception of Ethernet frames, the receive queue (or queues) must be ready, with
TX_EN. To enable flow control, Rx_Flow and Tx_Flow should also be set.
a ring, and pointed to by the TBASEn registers. A minimum of two buffer descriptors per ring is
required, unless the ring is disabled. Setting the ring to a size of one causes the same frame to be
transmitted twice. If TCP/IP off-load is to be enabled, the TxBD[TOE] bit must be set for each
frame.
its RxBD pointed to by the RBASEn registers. If TCP/IP off-load is to be enabled,
RCTRL[PRSDEP] must be set to the required off-load level. Both transmit and receive can be
gracefully stopped after transmission and reception begins.
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Hardware Controlled Initialization
User Initialization
Table 15-143. Steps for Minimum Register Initialization
1. Set and clear MACCFG1 [Soft_Reset]
2. Initialize MACCFG2
3. Initialize MAC station address
4. Set up the PHY using the MII Mgmt Interface
5. Configure the GMII
6. Clear IEVENT
7. Initialize IMASK
8. Initialize RCTRL
9. Initialize DMACTRL
Table 15-3
for the register list.
Description
Table 15-143
describes the minimum steps
Freescale Semiconductor
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