MPC8313CZQADDC Freescale Semiconductor, MPC8313CZQADDC Datasheet - Page 624

• Manufacturer Part Number: MPC8313CZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO EN EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313CZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

PCI Bus Interface
13.3.3.28 PCI Power Management Register 1 (PCIPMR1)
The PCI power management register 1 (PCIPMR1), shown in
software uses to manage the PCI controller’s power management state, as well as to enable and monitor
PMEs (power management events). This register can be accessed by the host in agent mode.
Table 13-44
13-42
Offset 0x84
Reset
Reset
31–24
18–16
W
W
15–8
Bits
R
R PME_
Bits
7–0
23
19
Status
31
15
0
0
describes the PCIPMR1 fields.
Data_Scale
NEXT_CAP_PTR
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
14
0
0
PME_Clock
BPCC_En
CAP_ID
Version
Name
Name
Data
13
0
0
Figure 13-46. PCI Power Management Register 1 (PCIPMR1)
12
0
0
Table 13-43. PCIPMR0 Field Descriptions (continued)
Data
Data_Select
Reports the state dependent data requested by the Data_Select field. The value of this field
is scaled by the value reported by the Data_Scale field.
Bus power/Clock control enable
0 Disable the bus power/clock control policies defined in section 4.7.1 of the PCI Bus
1 Enable the bus power/clock control policies defined in section 4.7.1 of the PCI Bus Power
Note: This bit field is not implemented, only required for all PCI-to-PCI Bridge
PME clock
0 Indicates that no PCI clock is required for the PCI controller to generate PME#
1 Indicates that PCI clock is required for the PCI controller to generate PME#
PCI Power Management Interface Specification version.
011 Revision 1.2 of the PCI Power Management Interface Specification
The next capability pointer points to the next item in the PCI controller’s capability list.
0000_0000 The end of the capability list
0000_0001 Indicates the power management support capability
0
0
Table 13-44. PCIPMR1 Field Descriptions
Power Management Interface Specification Revision 1.2
Management Interface Specification Revision 1.2
0
0
0
0
9
PME_
En
24
0
8
0
BPCC
_En
23
0
0
7
B2_B3
22
0
0
Figure
Description
Description
—
21
0
0
13-46, contains the bit fields that
0
0
4
No_Soft
_Reset
0
0
3
Freescale Semiconductor
—
Access: Read / write
—
0
2
0
Power_State
0
1
0
16
0
0
0