MPC8313CZQADDC Freescale Semiconductor, MPC8313CZQADDC Datasheet - Page 545

• Manufacturer Part Number: MPC8313CZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO EN EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313CZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

happen that a new command is issued to the NAND Flash device even when the device has not yet finished
processing the previous request. This may also result in unpredictable behavior.
10.5.5
Connecting the local bus UPM controller to a DRAM device requires a detailed examination of the timing
diagrams representing the possible memory cycles that must be performed when accessing this device.
This section describes timing diagrams for various UPM configurations for fast-page mode DRAM, with
LCRR[CLKDIV] = 4 or 8. These illustrative examples may not represent the timing necessary for any
specific device used with the eLBC. Here, LGPL1 is programmed to drive R/W of the DRAM, although
any LGPL
Freescale Semiconductor
n
Register
Interfacing to Fast-Page Mode DRAM Using UPM
signal may be used for this purpose.
FBAR
FBCR
FPAR
MDR
FCR
FIR
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Table 10-49. FCM Register Settings for Page Program (OR n [PGS] = 1)
(e.g. block 0x00010AB4)
locates page 5, buffer 1)
(e.g. 0x00005000
Initial Contents
0x41286DB0
0x80701000
0x00000000
block index
page offset
—
CMD0 = 0x80 = page address and data entry;
CMD1 = 0x70 = read status
CMD2 = 0x10 = program page;
BLK locates index of 128-Kbyte block
PI locates page index in BLK;
PI mod 2 indexes FCM buffer RAM;
MS = 0 and CI = 0
BC = 0 to write entire 2112-Byte page with ECC generation
returns with AS0 holding program status
OP0 = CM0 = command 0;
OP1 = CA = column address;
OP2 = PA = page address;
OP3 = WB = write data from buffer;
OP4 = CM2 = command 2;
OP5 = CW1 = wait on Flash ready and issue command 1;
OP6 = RS = read erase status into MDR[AS0];
OP7 = NOP
Description
Enhanced Local Bus Controller
10-97