MPC8313CZQADDC Freescale Semiconductor, MPC8313CZQADDC Datasheet - Page 349

• Manufacturer Part Number: MPC8313CZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO EN EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313CZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

The PowerPC architecture supports four types of interrupts:
7.3.4.2
As specified by the PowerPC architecture, all interrupts can be described as either precise or imprecise and
either synchronous or asynchronous. Asynchronous interrupts (some of which are maskable) are caused
by events external to the processor’s execution; synchronous interrupts, which are all handled precisely by
the e300 core, are caused by instructions. A system management interrupt is an implementation-specific
interrupt. The interrupt classes are shown in
Although interrupts have other characteristics, such as whether they are maskable, the distinctions shown
in
synchronous, imprecise instructions. While the PowerPC architecture supports imprecise handling of
floating-point exceptions, the core implements floating-point exception modes as precise.
Freescale Semiconductor
Table 7-6
•
•
•
•
Synchronous, precise—These are caused by instructions. All instruction-caused interrupts are
handled precisely; that is, the machine state at the time the interrupt occurs is known and can be
completely restored. This means that (excluding the trap and system call interrupts) the address of
the faulting instruction is provided to the interrupt handler and neither the faulting instruction nor
subsequent instructions in the code stream will complete execution before the interrupt is taken.
Once the interrupt is processed, execution resumes at the address of the faulting instruction (or at
an alternate address provided by the interrupt handler). When an interrupt is taken due to a trap or
system call instruction, execution resumes at an address provided by the handler.
Synchronous, imprecise—The PowerPC architecture defines two imprecise floating-point
exception modes: recoverable and nonrecoverable. Even though the core provides a means to
enable the imprecise modes, it implements these modes identically to the precise mode (that is, all
enabled floating-point exceptions are always precise on the core).
Asynchronous, maskable—The external system management interrupt (SMI) and decrementer
interrupts are maskable, asynchronous interrupts. When these interrupts occur, their handling is
postponed until the next instruction and any of its associated interrupts complete execution. If there
are no instructions in the execution units, the interrupt is taken immediately upon determination of
the correct restart address (for loading SRR0).
Asynchronous, nonmaskable—The system reset and the machine check interrupt are nonmaskable,
asynchronous interrupts. They may not be recoverable, or they may provide a limited degree of
recoverability. All interrupts report recoverability through MSR[RI].
define categories of interrupts that the core handles uniquely. Note that
Implementation-Specific Interrupt Model
Asynchronous, nonmaskable
Asynchronous, maskable
Synchronous
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Synchronous/Asynchronous
Table 7-6. Interrupt Classifications
Precise/Imprecise
Table
Imprecise
Precise
Precise
7-6.
Machine check
System reset
External interrupt
Decrementer
System management interrupt
Critical interrupt
Instruction-caused interrupts
Interrupt Type
e300 Processor Core Overview
Table 7-6
includes no
7-31