MPC8313CZQADDC Freescale Semiconductor, MPC8313CZQADDC Datasheet - Page 689

• Manufacturer Part Number: MPC8313CZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO EN EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313CZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

14.4.3.7
The AESU interrupt control register (AESUICR), shown in
errors. For a given error (as defined in
if the corresponding bit in this register is set, then the error is ignored; no error interrupt occurs and the
interrupt status register (AESUISR) is not updated to reflect the error. If the corresponding bit is not set,
then upon detection of an error, AESUISR is updated to reflect the error, causing assertion of the error
interrupt signal, and causing the module to halt processing.
Table 14-30
Freescale Semiconductor
0–48
Bits
Bits
61
62
63
49
50
51
52
Reset
Field
Addr
R/W
Name
Name
OFU
ERE
IFO
ICE
—
—
—
IE
describes the AESUICR fields.
AESU Interrupt Control Register (AESUICR)
0
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Input FIFO overflow. The shared symmetric Input FIFO has been pushed while full.
0 No error detected
1 Input FIFO has overflowed
Note: When operated through channel-controlled access, the SEC implements flow control, and FIFO size
Output FIFO underflow. The shared symmetric output FIFO has been read while empty.
0 No error detected
1 Output FIFO has underflow error
Reserved
Reserved
Integrity check error. The supplied ICV did not match the one computed by the MDEU.
0 Integrity check error enabled
1 Integrity check error disabled
Reserved
Internal error. An internal processing error was detected while the AESU was processing.
0 Internal error enabled
1 Internal error disabled
Early read error. The AESU IV register was read while the AESU was processing.
0 Early read error enabled
1 Early read error disabled
—
is not a limit to data input. When operated through host-controlled access, the AESU cannot accept
FIFO inputs larger than 256 bytes without overflowing.
Figure 14-32. AESU Interrupt Control Register (AESUICR)
Table 14-29. AESUISR Field Descriptions (continued)
48
ICE
49
Table 14-30. AESUICR Field Descriptions
—
50
Section 14.4.3.6, “AESU Interrupt Status Register
IE
51
ERE CE KSE DSE ME AE OFE IFE RSV IFO OFU —
52
AESU 0x3_4038
53
1000
R/W
Description
Description
54
Figure
55
56
14-32, controls the result of detected
57
58
59
60
Security Engine (SEC) 2.2
61
(AESUISR)”),
62
63
14-47