MPC8313CZQADDC Freescale Semiconductor, MPC8313CZQADDC Datasheet - Page 1107

• Manufacturer Part Number: MPC8313CZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO EN EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313CZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

17.5.8.1
In the slave transmitter routine, the received acknowledge bit (I2CnSR[RXAK]) must be tested before
sending the next byte of data. The master signals an end-of-data by not acknowledging the data transfer
from the slave. When no acknowledge is received (I2CnSR[RXAK] is set), the slave transmitter interrupt
routine must clear I2CnCR[MTX] to switch the slave from transmitter to receiver mode. A dummy read
of I2CnDR then releases SCLn so that the master can generate a STOP condition. See
17.5.8.2
When a master loses arbitration the following conditions all occur:
Thus, the slave interrupt service routine should first test I2CnSR[MAL] and software should clear it if it
is set. See
Freescale Semiconductor
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•
•
I2CnSR[MAL] is set
I2CnCR[MSTA] is cleared (changing the master to slave mode)
An interrupt occurs (if enabled) at the falling edge of the 9th clock of this transfer
Section 17.4.2.1, “Arbitration Control.”
Slave Transmitter and Received Acknowledge
Loss of Arbitration and Forcing of Slave Mode
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Figure
17-11.
I
2
C Interfaces
17-23