MPC8313CZQADDC Freescale Semiconductor, MPC8313CZQADDC Datasheet - Page 620

• Manufacturer Part Number: MPC8313CZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO EN EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313CZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

PCI Bus Interface
13.3.3.23 Maximum Latency Configuration Register
Figure 13-41
13.3.3.24 PCI Function Configuration Register
Figure 13-42
Table 13-40
13-38
Offset 0x44
Reset
Offset 0x3E
Offset 0x3F
Reset
Reset
W
15–6
Bits
W
W
R
3–4
R
R
5
1
15
0
7
7
CFG_LOCK Configuration lock. Controls access to the PCI configuration space from the PCI port. In host mode
shows the bit settings of the PCI function configuration register.
shows the maximum latency configuration register fields.
shows the PCI function configuration register fields.
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
0
Name
—
—
Table 13-40. PCI Function Configuration Register Field Descriptions
0
Reserved
the PCI configuration space is always inaccessible, so this bit is not used.
Normally, this bit will be cleared in agent mode once the configuration of the PCI controller is
complete to allow an external host to access the PCI configuration space.
0 Access to the configuration spaces is permitted.
1 Any inbound PCI access to the PCI configuration space is retried.
Reserved
6
Figure 13-41. Maximum Latency Configuration Register
Configuration Word Source,”
Figure 13-40. Minimum Grant Configuration Register
0
Figure 13-42. PCI Function Configuration Register
0
—
5
0
0
4
for more information on reset configuration.
MIN_GNT
MAX_LAT
All zeros
All zeros
0
0
Description
3
0
6
LOCK
CFG_
5
1
2
0
4
—
SeeSection 4.3.1.1, “Reset
cfg
3
Freescale Semiconductor
1
TLTD MLTD
Access: Read/Write
0
2
1
0
0
0
HA
cfg
0